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VLSI Architecture for MRF Based Stereo Matching

  • Sungchan Park
  • Chao Chen
  • Hong Jeong
Part of the Lecture Notes in Computer Science book series (LNCS, volume 4599)

Abstract

As a step towards real-time stereo on 2D markov random field (MRF), we will present fast belief propagation (FBP) VLSI architecture for stereo matching, which has a parallel, distributed and memory-efficient structure and lowest error rates among the real-time systems. FBP can reduce memory complexities by 17 times smaller than belief propagation (BP) and output 320x240 disparity image of 32 levels with 320 parallel processors on 2 Xilinx FPGAs at 30 frames/s. Multiple chips can be cascaded to increase computation speed due to its linear array architecture. Our structure is more adequate for high resolution and real-time applications like 3D video conference, multi-view coding and 3D modelling.

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References

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Copyright information

© Springer-Verlag Berlin Heidelberg 2007

Authors and Affiliations

  • Sungchan Park
    • 1
  • Chao Chen
    • 1
  • Hong Jeong
    • 1
  1. 1.Pohang University of Science and Technology, Electronic amd Electrical Engineering, Pohang, Kyungbuk, 790-784South Korea

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