Resource Conflict Detection in Simulation of Function Unit Pipelines

  • Pekka Jääskeläinen
  • Vladimír Guzma
  • Jarmo Takala
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 4599)


Processor simulators are important parts of processor design toolsets in which they are used to verify and evaluate the properties of the designed processors. While simulating architectures with independent function unit pipelines using simulation techniques that avoid the overhead of instruction bit-string interpretation, such as compiled simulation, the simulation of function unit pipelines can become one of the new bottlenecks for simulation speed.

This paper evaluates commonly used models for function unit pipeline resource conflict detection in processor simulation: a resource vector based-model, and an finite state automata (FSA) based model. In addition, an improvement to the simulation initialization time by means of lazy initialization of states in the FSA-based approach is proposed. The resulting model is faster to initialize and provides equal simulation speed when compared to the actively initialized FSA. Our benchmarks show at best 23 percent improvement to the initialization time.


Function Unit Design Space Exploration Finite State Automaton Instruction Schedule Simulation Speed 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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  1. 1.
    Corporaal, H.: Microprocessor Architectures: from VLIW to TTA. John Wiley & Sons, Chichester (1997)Google Scholar
  2. 2.
    Cmelik, B., Keppel, D.: Shade: a fast instruction-set simulator for execution profiling. In: Proc. SIGMETRICS 1994, Nashville, Tennessee, May 1994, pp. 128–137. ACM Press, New York (1994)CrossRefGoogle Scholar
  3. 3.
    Nohl, A., Braun, G., Schliebusch, O., Leupers, R., Meyr, H., Hoffmann, A.: A universal technique for fast and flexible instruction-set architecture simulation. In: Proc. DAC 2002, New Orleans, Louisiana, June 2002, pp. 22–27. ACM Press, New York (2002)CrossRefGoogle Scholar
  4. 4.
    Poncino, M., Zhu, J.: Dynamosim: a trace-based dynamically compiled instruction set simulator. In: Proc. ICCAD 2004, San Jose, CA, November 2004, pp. 131–136. IEEE/ACM Press, New York (2004)Google Scholar
  5. 5.
    Schnarr, E., Larus, J.R.: Fast out-of-order processor simulation using memoization. In: Proc. ASPLOS-VIII, San Jose, California, October 1998, pp. 283–294. ACM Press, New York (1998), doi:10.1145/291069.291063CrossRefGoogle Scholar
  6. 6.
    Schnarr, E.C., Hill, M.D., Larus, J.R.: Facile: a language and compiler for high-performance processor simulators. In: Proc. PLDI 2001, Snowbird, Utah, June 2001, pp. 321–331. ACM Press, New York (2001)CrossRefGoogle Scholar
  7. 7.
    Pees, S., Hoffmann, A., Meyr, H.: Retargeting of compiled simulators for digital signal processors using a machine description language. In: Proc. DATE 2000, Paris, France, March 2000, pp. 669–673. ACM Press, New York (2000)CrossRefGoogle Scholar
  8. 8.
    Pees, S., Hoffmann, A., Meyr, H.: Retargetable compiled simulation of embedded processors using a machine description language. ACM T. Des. Autom. Electron. Syst. 5(4), 815–834 (2000)CrossRefGoogle Scholar
  9. 9.
    Engel, F., Nührenberg, J., Fettweis, G.P.: A generic tool set for application specific processor architectures. In: Proc. CODES 2000, San Diego, CA, pp. 126–130. ACM Press, New York (2000)CrossRefGoogle Scholar
  10. 10.
    Kim, J.K., Kim, T.G.: Trace-driven rapid pipeline architecture evaluation scheme for asip design. In: Proc. ASPDAC 2003, Kitakyushu, Japan, pp. 129–134. ACM Press, New York (2003)CrossRefGoogle Scholar
  11. 11.
    Kim, H.Y., Kim, T.G.: Performance simulation modeling for fast evaluation of pipelined scalar processor by evaluation reuse. In: Proc. DAC 2005, San Diego, CA, June 2005, pp. 341–344. ACM Press, New York (2005)CrossRefGoogle Scholar
  12. 12.
    Davidson, E.S., Shar, L.E., Thomas, A.T., Fatel, J.H.: Effective control for pipelined computers. In: COMPCON75 Digest of Papers, February 1975, pp. 181–184. IEEE Computer Society Press, Los Alamitos (1975)Google Scholar
  13. 13.
    Faraboschi, P., Fisher, J.A., Young, C.: Instruction scheduling for instruction level parallel processors. In: Proc. IEEE, Washington, DC, vol. 89, pp. 1638–1659. IEEE Computer Society Press, Los Alamitos (2001)Google Scholar
  14. 14.
    Bradlee, D.G., Henry, R.R., Eggers, S.J.: The marion system for retargetable instruction scheduling. In: Proc. PLDI 1991, Toronto, Ontario, Canada, June 1991, pp. 229–240. ACM Press, New York (1991)CrossRefGoogle Scholar
  15. 15.
    Cormen, T.H., Leiserson, C.E., R.L.R.: Introduction to Algorithms. The MIT Press, Cambridge, Massachusetts (1999)Google Scholar
  16. 16.
    Jääskeläinen, P.: Instruction Set Simulator for Transport Triggered Architectures. Master’s thesis, Department of Information Technology, Tampere University of Technology, Tampere, Finland, P.O.Box 553, FIN-33101 Tampere, Finland (Sepember 2005), See
  17. 17.
    Bala, V., Rubin, N.: Efficient instruction scheduling using finite state automata. Int. Journal of Parallel Programming 25(2), 53–82 (1997)Google Scholar
  18. 18.
    Hennessy, J.L., Patterson, D.A.: Computer Architecture: A Quantitative Approach, 3rd edn. Morgan Kaufmann Publishers, San Francisco (2003)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2007

Authors and Affiliations

  • Pekka Jääskeläinen
    • 1
  • Vladimír Guzma
    • 1
  • Jarmo Takala
    • 1
  1. 1.Department of Information Technology, Tampere University of Technology, P.O. Box 553, FIN-33101 TampereFinland

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