Resource Conflict Detection in Simulation of Function Unit Pipelines

  • Pekka Jääskeläinen
  • Vladimír Guzma
  • Jarmo Takala
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 4599)

Abstract

Processor simulators are important parts of processor design toolsets in which they are used to verify and evaluate the properties of the designed processors. While simulating architectures with independent function unit pipelines using simulation techniques that avoid the overhead of instruction bit-string interpretation, such as compiled simulation, the simulation of function unit pipelines can become one of the new bottlenecks for simulation speed.

This paper evaluates commonly used models for function unit pipeline resource conflict detection in processor simulation: a resource vector based-model, and an finite state automata (FSA) based model. In addition, an improvement to the simulation initialization time by means of lazy initialization of states in the FSA-based approach is proposed. The resulting model is faster to initialize and provides equal simulation speed when compared to the actively initialized FSA. Our benchmarks show at best 23 percent improvement to the initialization time.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2007

Authors and Affiliations

  • Pekka Jääskeläinen
    • 1
  • Vladimír Guzma
    • 1
  • Jarmo Takala
    • 1
  1. 1.Department of Information Technology, Tampere University of Technology, P.O. Box 553, FIN-33101 TampereFinland

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