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Designing Verification Conditions for Software

  • K. Rustan M. Leino
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 4603)

Abstract

Software verification technology has the potential to improve the quality of software. The basic technique is to generate verification conditions for a given program and to discharge these proof obligations using a theorem prover. Encoding the verification conditions is a delicate process, not just because it must capture the intended programming semantics, but also because it must yield formulas that a theorem prover can process effectively.

In this talk, I will discuss the process of generating verification conditions in the program verifier for the object-oriented language Spec#. I will highlight design decisions we have made in modeling programs and targeting SMT solvers, lessons we have learned, and challenges that remain ahead.

Copyright information

© Springer-Verlag Berlin Heidelberg 2007

Authors and Affiliations

  • K. Rustan M. Leino
    • 1
  1. 1.Microsoft Research, Redmond, WAUSA

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