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On Synthesizing Controllers from Bounded-Response Properties

  • Oded Maler
  • Dejan Nickovic
  • Amir Pnueli
Part of the Lecture Notes in Computer Science book series (LNCS, volume 4590)

Abstract

In this paper we propose a complete chain for synthesizing controllers from high-level specifications. From real-time properties expressed in the logic mtl we generate, under bounded-variability assumptions, deterministic timed automata to which we apply safety synthesis algorithms to derive a controller that satisfies the properties by construction. Some preliminary experimental results are reported.

Keywords

Temporal Logic Discrete Event System Liveness Property Synthesis Algorithm Controller Synthesis 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

References

  1. [AT02]
    Altisen, K., Tripakis, S.: Tools for Controller Synthesis of Timed Systems. In: RT-TOOLS 2002 (2002)Google Scholar
  2. [AD94]
    Alur, R., Dill, D.L.: A Theory of Timed Automata. Theoretical Computer Science 126, 183–235 (1994)zbMATHCrossRefGoogle Scholar
  3. [AFH96]
    Alur, R., Feder, T., Henzinger, T.A.: The Benefits of Relaxing Punctuality (first published in PODC’91). Journal of the ACM 43, 116–146 (1996)zbMATHCrossRefGoogle Scholar
  4. [A04]
    Asarin, E.: Challenges in Timed Languages. Bulletin of EATCS 83 (2004)Google Scholar
  5. [ACM02]
    Asarin, E., Caspi, P., Maler, O.: Timed Regular Expressions. The Journal of the ACM 49, 172–206 (2002)CrossRefGoogle Scholar
  6. [AMP95]
    Asarin, E., Maler, O., Pnueli, A.: Symbolic Controller Synthesis for Discrete and Timed Systems. In: Antsaklis, P.J., Kohn, W., Nerode, A., Sastry, S.S. (eds.) Hybrid Systems II. LNCS, vol. 999, pp. 1–20. Springer, Heidelberg (1995)Google Scholar
  7. [BL69]
    Buchi, J.R., Landweber, L.H.: Solving Sequential Conditions by Finite-state Operators. Trans. of the AMS 138, 295–311 (1969)zbMATHCrossRefGoogle Scholar
  8. [CDF+05]
    Cassez, F., David, A., Fleury, E., Larsen, K.G., Lime, D.: Efficient On-the-Fly Algorithms for the Analysis of Timed Games. In: Abadi, M., de Alfaro, L. (eds.) CONCUR 2005. LNCS, vol. 3653, pp. 66–80. Springer, Heidelberg (2005)CrossRefGoogle Scholar
  9. [Chu63]
    Church, A.: Logic, Arithmetic and Automata. In: Proc. of the Int. Cong. of Mathematicians 1962, pp. 23-35 (1963)Google Scholar
  10. [KP05]
    Kesten, Y., Pnueli, A.: A Compositional Approach to CTL* Verification. Theoretical Computer Science 331, 397–428 (2005)zbMATHCrossRefGoogle Scholar
  11. [KY03]
    Kloukinas, C., Yovine, S.: Synthesis of Safe, QoS Extendible, Application Specific Schedulers for Heterogeneous Real-Time Systems. In: ECRTS 2003, pp. 287–294 (2003)Google Scholar
  12. [Koy90]
    Koymans, R.: Specifying Real-time Properties with Metric Temporal Logic. Real-time Systems 2, 255–299 (1990)CrossRefGoogle Scholar
  13. [M07]
    Maler, O.: On Optimal and Reasonable Control in the Presence of Adversaries. In: Annual Reviews in Control (2007)Google Scholar
  14. [MN04]
    Maler, O., Nickovic, D.: Monitoring Temporal Properties of Continuous Signals. In: Lakhnech, Y., Yovine, S. (eds.) FORMATS 2004 and FTRTFT 2004. LNCS, vol. 3253, pp. 152–166. Springer, Heidelberg (2004)Google Scholar
  15. [MNP05]
    Maler, O., Nickovic, D., Pnueli, A.: Real Time Temporal Logic: Past, Present, Future. In: Pettersson, P., Yi, W. (eds.) FORMATS 2005. LNCS, vol. 3829, pp. 2–16. Springer, Heidelberg (2005)CrossRefGoogle Scholar
  16. [MNP06]
    Maler, O., Nickovic, D., Pnueli, A.: From MITL to Timed Automata. In: Asarin, E., Bouyer, P. (eds.) FORMATS 2006. LNCS, vol. 4202, pp. 274–289. Springer, Heidelberg (2006)CrossRefGoogle Scholar
  17. [MP04]
    Maler, O., Pnueli, A.: On Recognizable Timed Languages. In: Walukiewicz, I. (ed.) FOSSACS 2004. LNCS, vol. 2987, pp. 348–362. Springer, Heidelberg (2004)Google Scholar
  18. [MPS95]
    Maler, O., Pnueli, A., Sifakis, J.: On the Synthesis of Discrete Controllers for Timed Systems. In: Mayr, E.W., Puech, C. (eds.) STACS 1995. LNCS, vol. 900, pp. 229–242. Springer, Heidelberg (1995)Google Scholar
  19. [PPS06]
    Piterman, N., Pnueli, A., Sa’ar, Y.: Synthesis of Reactive(1) Designs. In: Emerson, E.A., Namjoshi, K.S. (eds.) VMCAI 2006. LNCS, vol. 3855, pp. 364–380. Springer, Heidelberg (2005)CrossRefGoogle Scholar
  20. [PP06]
    Piterman, N., Pnueli, A.: Faster Solutions of Rabin and Streett Games. In: LICS 2006, pp. 275–284 (2006)Google Scholar
  21. [PR89]
    Pnueli, A., Rosner, R.: On the Synthesis of a Reactive Module. In: POPL 1989, pp. 179–190 (1989)Google Scholar
  22. [RW89]
    Ramadge, P.J., Wonham, W.M.: The Control of Discrete Event Systems. Proc. of the IEEE 77, 81–98 (1989)CrossRefGoogle Scholar
  23. [TB73]
    Trakhtenbrot, B.A., Barzdin, Y.M.: Finite Automata: Behavior and Synthesis. North-Holland, Amsterdam (1973)zbMATHGoogle Scholar
  24. [T02]
    Tripakis, S.: Fault Diagnosis for Timed Automata. In: Damm, W., Olderog, E.-R. (eds.) FTRTFT 2002. LNCS, vol. 2469, pp. 205–224. Springer, Heidelberg (2002)CrossRefGoogle Scholar
  25. [TA99]
    Tripakis, S., Altisen, K.: On-the-Fly Controller Synthesis for Discrete and Timed Systems, FM’99 1999. In: Woodcock, J.C.P., Davies, J., Wing, J.M. (eds.) FM 1999. LNCS, vol. 1709, Springer, Heidelberg (1999)Google Scholar
  26. [TY01]
    Tripakis, S., Yovine, S.: Analysis of Timed Systems using Time-abstracting Bisimulations. Formal Methods in System Design 18, 25–68 (2001)zbMATHCrossRefGoogle Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2007

Authors and Affiliations

  • Oded Maler
    • 1
  • Dejan Nickovic
    • 1
  • Amir Pnueli
    • 2
    • 3
  1. 1.Verimag, 2 Av. de Vignate, 38610 GièresFrance
  2. 2.Weizmann Institute of Science, Rehovot 76100Israel
  3. 3.New York University, 251 Mercer St. New York, NY 10012USA

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