High Performance Implementation of an FPGA-Based Sequential DT-CNN
In this paper an FPGA-based implementation of a sequential discrete time cellular neural network (DT-CNN) with 3×3 templates is described. The architecture is based on a single pipelined cell which is employed to emulate a CNN with larger number of neurons. This solution diminishes the use of hardware resources on the FPGA and allows the cell to process real time input data in a sequential mode. Highly efficient FPGA implementation has been achieved by manual design based on low level instantiation and placement of hardware primitives. The Intellectual Property Core offers an appropriate tradeoff between area and speed. Our architecture has been developed to assist designers implementing discrete CNN models with performance equivalent to hundreds or millions of neurons on low cost FPGA-based systems.
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