FPGA Implementation of kNN Classifier Based on Wavelet Transform and Partial Distance Search

  • Yao-Jung Yeh
  • Hui-Ya Li
  • Wen-Jyi Hwang
  • Chiung-Yao Fang
Part of the Lecture Notes in Computer Science book series (LNCS, volume 4522)


A novel algorithm for field programmable gate array (FPGA) realization of kNN classifier is presented in this paper. The algorithm identifies first k closest vectors in the design set of a kNN classifier for each input vector by performing the partial distance search (PDS) in the wavelet domain. It employs subspace search, bitplane reduction and multiple-coefficient accumulation techniques for the effective reduction of the area complexity and computation latency. The proposed implementation has been embedded in a softcore CPU for physical performance measurement. Experimental results show that the implementation provides a cost-effective solution to the FPGA realization of kNN classification systems where both high throughput and low area cost are desired.


FPGA Implementation Partial Distance Search Image Processing Pattern Recognition Nonparametric Classification 


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Copyright information

© Springer Berlin Heidelberg 2007

Authors and Affiliations

  • Yao-Jung Yeh
    • 1
  • Hui-Ya Li
    • 1
  • Wen-Jyi Hwang
    • 1
  • Chiung-Yao Fang
    • 1
  1. 1.Graduate Institute of Computer Science and Information Engineering, National Taiwan Normal University, Taipei, 117Taiwan

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