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IAF Neuron Implementation for Mixed-Signal PCNN Hardware

  • Tim Kaulmann
  • Sven Lütkemeier
  • Ulrich Rückert
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 4507)

Abstract

In this paper, the implementation results of an integrate and fire neuron implemented in a 130 nm process are presented. This publication covers the properties of IAF neurons from calculations on an ideal electrical circuit modeling the soma of an IAF neuron and compares the theoretical results with simulation results from an extracted layout of the implemented neuron.

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References

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    Matolin, D., Schreiter, J., Getzlaff, S., Schüffny, R.: An Analog VLSI Pulsed Neural Network Implementation for Image Segmentation. In: Proc. of the International Conference on Parallel Computing in Electrical Engineering, pp. 51–55 (2004)Google Scholar
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    Indiveri, G., Chicca, E., Douglas, R.: A VLSI Array of Low-Power Spiking Neurons and Bistable Synapses With Spike-Timing Dependent Plasticity. IEEE Transactions on Neural Networks 17(1), 211–221 (2004)CrossRefGoogle Scholar
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    Liu, S.-C., Kramer, J., Indiveri, G., Delbrück, T., Douglas, R.: Orientation-selective a VLSI Spiking Neurons. Neural Networks 14, 629–643 (2001)CrossRefGoogle Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2007

Authors and Affiliations

  • Tim Kaulmann
    • 1
  • Sven Lütkemeier
    • 1
  • Ulrich Rückert
    • 1
  1. 1.Heinz Nixdorf Institute, System and Circuit Technology, University of Paderborn, Fuerstenallee 11, 33102 PaderbornGermany

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