On Control Signals for Multi-Dimensional Time

  • DaeGon Kim
  • Gautam
  • S. Rajopadhye
Part of the Lecture Notes in Computer Science book series (LNCS, volume 4382)


Affine control loops (acls) comprise an important class of compute- and data-intensive computations. The theoretical framework for the automatic parallelization of acls is well established. However, the hardware compilation of arbitrary acls is still in its infancy. An important component for an efficient hardware implementation is a control mechanism that informs each processing element (pe) which computation needs to be performed and when.

We formulate this control signal problem in the context of compiling arbitrary acls parallelized with a multi-dimensional schedule into hardware. We characterize the logical time instants when pes need a control signal indicating which particular computations need to be performed. Finally, we present an algorithm to compute the minimal set of logical time instants for these control signals.


Control Signal Iteration Space Loop Nest Systolic Array Parallel Loop 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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  1. 1.
    Bastoul, C., et al.: Putting polyhedral loop transformations to work. In: Rauchwerger, L. (ed.) LCPC 2003. LNCS, vol. 2958, pp. 209–225. Springer, Heidelberg (2004)Google Scholar
  2. 2.
    Schreiber, R., et al.: Pico-npa: High level synthesis of nonprogrammable hardware accelerators (preliminary version presented at ASAP 2000). Journal of VLSI SIgnal Processing (to appear, 2001)Google Scholar
  3. 3.
    Guillou, A.-C., et al.: Hardware design methodology with the alpha language. In: FDL’01 (2001)Google Scholar
  4. 4.
    Feautrier, P.: Some efficient solutions to the affine scheduling problem: Part II. multidimensional time. Int. J. of Parallel Program. 21(6), 389–420 (1992)zbMATHCrossRefMathSciNetGoogle Scholar
  5. 5.
    Feautrier, P.: Some efficient solutions to the affine scheduling problem: Part I. one-dimensional time. Int. J. of Parallel Program. 21(5), 313–348 (1992)zbMATHCrossRefMathSciNetGoogle Scholar
  6. 6.
    Guillou, A.-C., Quinton, P., Risset, T.: Hardware synthesis for multi-dimensional time. In: ASAP 2003, pp. 40–50 (2003)Google Scholar
  7. 7.
    Gupta, G., Renganarayana, L., Rajopadhye, S.: GRAIL: A generic reconfigurable affine interconnection lattice (submitted 2006)Google Scholar
  8. 8.
    Feautrier, P.: Dataflow analysis of array and scalar references. Int. J. of Parallel Programming 20(1), 23–53 (1991)zbMATHCrossRefGoogle Scholar
  9. 9.
    Pugh, W.: A practical algorithm for exact array dependence analysis. Communications of the ACM 35(8), 102–114 (1992)CrossRefGoogle Scholar
  10. 10.
    Karp, R.M., Miller, R.E., Winograd, S.V.: The organization of computations for uniform recurrence equations. JACM 14(3), 563–590 (1967)zbMATHCrossRefMathSciNetGoogle Scholar
  11. 11.
    Lamport, L.: The parallel execution of DO loops. Communications of the ACM, 83–93 (1974)Google Scholar
  12. 12.
    Darte, A., Robert, Y., Vivien, F.: Scheduling and Automatic Parallelization. Birkhäuser, Basel (2000)zbMATHGoogle Scholar
  13. 13.
    Rajopadhye, S.V., Purushothaman, S., Fujimoto, R.: On synthesizing systolic arrays from recurrence equations with linear dependencies (Later appeared in Parallel Computing, June 1990). In: Foundations of Software Technology and Theoretical Computer Science, vol. 241, pp. 488–503 (1986)Google Scholar
  14. 14.
    Quinton, P., Van Dongen, V.: The mapping of linear equations on regular arrays. J. of VLSI Signal Processing 1(2), 95–113 (1989)zbMATHCrossRefGoogle Scholar
  15. 15.
    Gupta, G., Rajopadhye, S., Quinton, P.: Scheduling reductions on realistic machines. In: SPAA ’02: Symposium on Parallel algorithms and architectures, Winnipeg, Manitoba, Canada, pp. 117–126 (2002)Google Scholar
  16. 16.
    Lim, A.W., Cheong, G.I., Lam, M.S.: An affine partitioning algorithm to maximize parallelism and minimize communication. In: Int. Conf. on Supercomputing, pp. 228–237 (1999)Google Scholar
  17. 17.
    Kuck, D.L.: Structure of Computers and Computations. John Wiley & Sons, Inc., New York (1978)Google Scholar
  18. 18.
    Bagnara, R., Hill, P.M., Zaffanella, E.: The Parma Polyhedra Library User’s Manual. Dept of Mathematics, University of Parma, Parma, Italy. version 0.9 edn. (2006), Available at
  19. 19.
    Wilde, D.: A library for doing polyhedral operations. Technical Report PI-785, IRISA (1993)Google Scholar
  20. 20.
    Boulet, P., Feautrier, P.: Scanning polyhedra without do-loops. In: PACT’1998, pp. 4–11 (1998)Google Scholar
  21. 21.
    Bowden, S., Wilde, D., Rajopadhye, S.V.: Quadratic control signals in linear systolic arrays. In: ASAP 2000, pp. 268–275 (2000)Google Scholar

Copyright information

© Springer Berlin Heidelberg 2007

Authors and Affiliations

  • DaeGon Kim
    • 1
  • Gautam
    • 1
    • 2
  • S. Rajopadhye
    • 1
  1. 1.Colorado State University, Fort Collins, COU.S.A.
  2. 2.IRISA, RennesFrance

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