VCEGAR: Verilog CounterExample Guided Abstraction Refinement

  • Himanshu Jain
  • Daniel Kroening
  • Natasha Sharygina
  • Edmund Clarke
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 4424)


As first step, most model checkers used in the hardware industry convert a high-level register transfer language (RTL) design into a netlist. However, algorithms that operate at the netlist level are unable to exploit the structure of the higher abstraction levels, and thus, are less scalable. The RTL level of a hardware description language such as Verilog is similar to a software program with special features for hardware design such as bit-vector arithmetic and concurrency. We describe a hardware model checking tool, VCEGAR, which performs verification at the RTL level using software verification techniques. It implements predicate abstraction and a refinement loop as used in software verification. The novel aspects are the generation of new word-level predicates, an efficient predicate image computation in presence of a large number of predicates, and precise modeling of the bit-vector semantics of hardware designs.




  1. 1.
    Graf, S., Saïdi, H.: Construction of abstract state graphs with PVS. In: Grumberg, O. (ed.) CAV 1997. LNCS, vol. 1254, pp. 72–83. Springer, Heidelberg (1997)Google Scholar
  2. 2.
    Ball, T., Rajamani, S.: Boolean programs: A model and process for software analysis. Technical Report 2000-14, Microsoft Research (2000)Google Scholar
  3. 3.
    Kurshan, R.: Computer-Aided Verification of Coordinating Processes. Princeton University Press, Princeton (1995)MATHGoogle Scholar
  4. 4.
    Clarke, E.M., et al.: Counterexample-guided abstraction refinement. In: Emerson, E.A., Sistla, A.P. (eds.) CAV 2000. LNCS, vol. 1855, pp. 154–169. Springer, Heidelberg (2000)CrossRefGoogle Scholar
  5. 5.
    Clarke, E., et al.: SAT Based Predicate Abstraction for Hardware Verification. In: Giunchiglia, E., Tacchella, A. (eds.) SAT 2003. LNCS, vol. 2919, pp. 78–92. Springer, Heidelberg (2004)Google Scholar
  6. 6.
    Clarke, E., Jain, H., Kroening, D.: Predicate Abstraction and Refinement Techniques for Verifying Verilog. Technical Report CMU-CS-04-139 (2004)Google Scholar
  7. 7.
    Jain, H., et al.: Word level predicate abstraction and refinement for verifying RTL. In: DAC, pp. 445–450 (2005)Google Scholar
  8. 8.
    Clarke, E., et al.: Predicate abstraction of ANSI–C programs using SAT. Formal Methods in System Design 25, 105–127 (2004)MATHCrossRefGoogle Scholar

Copyright information

© Springer Berlin Heidelberg 2007

Authors and Affiliations

  • Himanshu Jain
    • 1
  • Daniel Kroening
    • 2
  • Natasha Sharygina
    • 1
    • 3
  • Edmund Clarke
    • 1
  1. 1.Carnegie Mellon University, School of Computer Science 
  2. 2.ETH ZuerichSwitzerland
  3. 3.Informatics Department, University of Lugano 

Personalised recommendations