VCEGAR: Verilog CounterExample Guided Abstraction Refinement

  • Himanshu Jain
  • Daniel Kroening
  • Natasha Sharygina
  • Edmund Clarke
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 4424)

Abstract

As first step, most model checkers used in the hardware industry convert a high-level register transfer language (RTL) design into a netlist. However, algorithms that operate at the netlist level are unable to exploit the structure of the higher abstraction levels, and thus, are less scalable. The RTL level of a hardware description language such as Verilog is similar to a software program with special features for hardware design such as bit-vector arithmetic and concurrency. We describe a hardware model checking tool, VCEGAR, which performs verification at the RTL level using software verification techniques. It implements predicate abstraction and a refinement loop as used in software verification. The novel aspects are the generation of new word-level predicates, an efficient predicate image computation in presence of a large number of predicates, and precise modeling of the bit-vector semantics of hardware designs.

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Copyright information

© Springer Berlin Heidelberg 2007

Authors and Affiliations

  • Himanshu Jain
    • 1
  • Daniel Kroening
    • 2
  • Natasha Sharygina
    • 1
    • 3
  • Edmund Clarke
    • 1
  1. 1.Carnegie Mellon University, School of Computer Science 
  2. 2.ETH ZuerichSwitzerland
  3. 3.Informatics Department, University of Lugano 

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