A Low Power Compression Processor for Body Sensor Network System

Conference paper
Part of the IFMBE Proceedings book series (IFMBE, volume 13)

Abstract

A low power 16-bit RISC is proposed for body sensor network system. The RISC is designed of basic 3 stage pipeline architecture which has 28 instruction sets. Some special instructions are proposed for efficient applications. The lossless compression accelerator is embedded in the RISC to support the low energy data compression. The accelerator consists of 16×16-bit storage array which has vertical and horizontal access path. By using the accelerator the energy consumption of the lossless compression operation is reduced by 95%. The RISC is implemented by 1-poly 6-metal 0.18um CMOS technology with 16k gates. It operates at 4MHz and consumes 24.2uW at 0.6V supply voltage.

Keywords

Body Sensor Network RISC Lossless Compression 

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Copyright information

© International Federation for Medical and Biological Engineering 2007

Authors and Affiliations

  1. 1.KAISTDaejeonKorea
  2. 2.Semiconductor System Laboratory Department of Electrical Engineering and Computer ScienceKAISTDaejeonKorea

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