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Verifying VHDL Designs with Multiple Clocks in SMV

  • A. Smrčka
  • V. Řehák
  • T. Vojnar
  • D. Šafránek
  • P. Matoušek
  • Z. Řehák
Part of the Lecture Notes in Computer Science book series (LNCS, volume 4346)

Abstract

The paper considers the problem of model checking real-life VHDL-based hardware designs via their automated transformation to a model verifiable using the SMV model checker. In particular, model checking of asynchronous designs, i.e., designs driven by multiple clocks, is discussed. Two original approaches to compiling asynchronous VHDL designs to the SMV language such that errors possibly arising from the asynchronicity are preserved are proposed. The paper also presents results of experiments with using the proposed methods for verification of several real-life asynchronous components of an FPGA-based router being developed within the Liberouter project.

Keywords

Model Check Critical Path Clock Signal Hardware Design Combinational Logic 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer Berlin Heidelberg 2007

Authors and Affiliations

  • A. Smrčka
    • 1
  • V. Řehák
    • 2
  • T. Vojnar
    • 1
  • D. Šafránek
    • 2
  • P. Matoušek
    • 1
  • Z. Řehák
    • 2
  1. 1.FIT BUT, BrnoCzech Republic
  2. 2.FI MU, BrnoCzech Republic

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