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Fifteen Years of Formal Property Verification in Intel

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25 Years of Model Checking

Part of the book series: Lecture Notes in Computer Science ((LNTCS,volume 5000))

Abstract

Model checking technologies have been applied to hardware verification in the last 15 years. Pioneering work has been conducted in Intel since 1990 using model checking technologies to build industrial hardware verification systems. This paper reviews the evolution and the success of these systems in Intel and in particular it summarizes the many challenges and learning that have resulted from changing how hardware validation is performed in Intel to include formal property verification. The paper ends with a discussion on how the learning from hardware verification can be used to accelerate the industrial deployment of model-checking technologies for software verification.

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References

  1. Kamhi, G., Weissberg, O., Fix, L., Binyamini, Z., Shtadler, Z.: Automatic data-path extraction for efficient usage of HDD. In: Grumberg, O. (ed.) CAV 1997. LNCS, vol. 1254, pp. 95–106. Springer, Heidelberg (1997)

    Google Scholar 

  2. Kamhi, G., Fix, L.: Adaptive variable reordering for symbolic model checking. In: IEEE/ACM International Conference on Computer Aided Design (ICCAD) (1998)

    Google Scholar 

  3. Kamhi, G., Fix, L., Binyamini, Z.: Symbolic Model Checking Visualization. In: Gopalakrishnan, G.C., Windley, P. (eds.) FMCAD 1998. LNCS, vol. 1522, pp. 290–302. Springer, Heidelberg (1998)

    Chapter  Google Scholar 

  4. Mador-Haim, S., Fix, L.: Inputs elimination and data abstraction in model checking. In: Gopalakrishnan, G.C., Windley, P. (eds.) FMCAD 1998. LNCS, vol. 1522. Springer, Heidelberg (1998)

    Chapter  Google Scholar 

  5. Fraer, R., Kamhi, G., Fix, L., Vardi, M.: Evaluating Semi-Exhaustive Verification Techniques for Bug Hunting. In: SMC, 1999 (CAV 1999 workshop) (1999)

    Google Scholar 

  6. Fraer, R., Kamhi, G., Ziv, B., Vardi, M.Y., Fix, L.: Prioritized Traversal: Efficient Reachability Analysis for Verification and Falsification. In: CAV (2000)

    Google Scholar 

  7. Vardi, M.Y., Giunchiglia, E., Tacchella, A., Kamhi, G., Fix, L., Fraer, R., Copty, F.: Benefits of Bounded Model Checking at an Industrial Setting. In: Berry, G., Comon, H., Finkel, A. (eds.) CAV 2001. LNCS, vol. 2102. Springer, Heidelberg (2001)

    Google Scholar 

  8. Hazelhurst, S., Wiessberg, O., Kamhi, G., Fix, L.: A hybrid verification approach: getting deep into the design. In: DAC 2002 (2002)

    Google Scholar 

  9. Armoni, R., Fix, L., Flaisher, A., Gerth, R., Ginsburg, B., Kanza, T., Landver, A., Mador-Haim, S., Singerman, E., Tiemeyer, A., Vardi, M., Zbar, Y.: The ForSpec temporal Logic: A new Temporal Property Specification Language. In: Katoen, J.-P., Stevens, P. (eds.) ETAPS 2002 and TACAS 2002. LNCS, vol. 2280, pp. 296–311. Springer, Heidelberg (2002)

    Chapter  Google Scholar 

  10. Vardi, M.Y., Grumberg, O., Armoni, R., Piterman, N., Fix, L., Flaisher, A., Tiemeyer, A.: Enhanced Vacuity Detection in Linear Temporal Logic. In: Hunt Jr., W.A., Somenzi, F. (eds.) CAV 2003. LNCS, vol. 2725, pp. 368–380. Springer, Heidelberg (2003)

    Google Scholar 

  11. Basu, P., Das, S., Dasgupta, P., Chakrabarti, P.P., Mohan, C.R., Fix, L.: Formal Verification Coverage: are the RTL-properties covering the design’s architectural intent. In: DATE 2004, pp. 668–669 (2004)

    Google Scholar 

  12. Basu, P., Das, S., Dasgupta, P., Chakrabarti, P.P., Mohan, C.R., Fix, L.: Formal Verification Coverage: Computing the coverage gap between temporal specifications. In: ICCAD 2004 (2004)

    Google Scholar 

  13. Armoni, R., Fix, L., Fraer, R., Huddleston, S., Piterman, N., Vardi, M.: SAT-based induction for temporal safety properties. In: BMC workshop at CAV 2004 (2004)

    Google Scholar 

  14. Basu, P., Das, S., Dasgupta, P., Chakrabarti, P.P., Mohan, C.R., Fix, L.: Formal methods for analyzing the completeness of assertions suite against a high level fault model. In: VLSI Design 2005 conference at Kokata (to be published)

    Google Scholar 

  15. Arons, T., Elster, E., Fix, L., Mador-Haim, S., Mishaeli, M., Shalev, J., Singerman, E., Tiemeyer, A., Vardi, M., Zuck, L.: Formal Verification of Backward compatibility of Microcode. In: 17th International Conference on Computer Aided Verification, Edinburgh (July 2005)

    Google Scholar 

  16. Fix, L., Grumberg, O., Heyman, T., Schuster, A.: Verifying very large industrial circuits using 100 processes and beyond. In: Third International Symposium on Automated Technology for Verification and Analysis (October 2005) Best paper award

    Google Scholar 

  17. McMillan, K.L.: Symbolic Model Checking: an approach to the state explosion problem, PhD Thesis. CMU CS-929131 (1992)

    Google Scholar 

  18. Pnueli, A.: The temporal logic of programs. In: Proc. 18th IEEE Symposium on Foundation of Computer Science (1977)

    Google Scholar 

  19. Clarke, E., Grumberg, O., Hamaguchi, H.: Another Look at LTL Model Checking. Formal Methods in System Design 10(1) (February 1997); In: Dill, D.L. (ed.) CAV 1994. LNCS, vol. 818. Springer, Heidelberg (1994)

    Google Scholar 

  20. Pnueli, A.: In Transition from Global to Modular Temporal Reasoning about Programs. In: Apt, K.R. (ed.) Logics and Models of Concurrent Systems. sub-series F: Computer and System Science, pp. 123–144. Springer (1985)

    Google Scholar 

  21. Clarke, E., Biere, A., Cimatti, A., Zhu, Y.: Symbolic Model Checking without BDDs. In: Cleaveland, W.R. (ed.) ETAPS 1999 and TACAS 1999. LNCS, vol. 1579. Springer, Heidelberg (1999)

    Google Scholar 

  22. Bryant, R.E., Seger, C.-J.: Formal verification of digital circuits using symbolic ternary system models. In: Clarke, E.M., Kurshan, R.P. (eds.) CAV 1990. LNCS, vol. 531. Springer (1990)

    Google Scholar 

  23. Vardi, M.: From Church and Prior to PSL: Standing on The Shoulders of Giants. This volume

    Google Scholar 

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Orna Grumberg Helmut Veith

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Fix, L. (2008). Fifteen Years of Formal Property Verification in Intel. In: Grumberg, O., Veith, H. (eds) 25 Years of Model Checking. Lecture Notes in Computer Science, vol 5000. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-69850-0_8

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  • DOI: https://doi.org/10.1007/978-3-540-69850-0_8

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-69849-4

  • Online ISBN: 978-3-540-69850-0

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