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Leveraging High Performance Data Cache Techniques to Save Power in Embedded Systems

  • Major Bhadauria
  • Sally A. McKee
  • Karan Singh
  • Gary S. Tyson
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 4367)

Abstract

Voltage scaling reduces leakage power for cache lines unlikely to be referenced soon. Partitioning reduces dynamic power via smaller, specialized structures. We combine approaches, adding a voltage scaling design providing finer control of power budgets. This delivers good performance and low power, consuming 34% of the power of previous designs.

Keywords

Dynamic Power Cache Line Leakage Power Reuse Distance Dynamic Power Consumption 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer Berlin Heidelberg 2007

Authors and Affiliations

  • Major Bhadauria
    • 1
  • Sally A. McKee
    • 1
  • Karan Singh
    • 1
  • Gary S. Tyson
    • 2
  1. 1.Computer Systems Lab, School of Electrical and Computer Engineering, Cornell University 
  2. 2.Department of Computer Science, Florida State University 

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