Compiler Supports and Optimizations for PAC VLIW DSP Processors

  • Yung-Chia Lin
  • Chung-Lin Tang
  • Chung-Ju Wu
  • Ming-Yu Hung
  • Yi-Ping You
  • Ya-Chiao Moo
  • Sheng-Yuan Chen
  • Jenq-Kuen Lee
Part of the Lecture Notes in Computer Science book series (LNCS, volume 4339)

Abstract

PAC DSP is a novel VLIW DSP processor exceedingly utilized with port-restricted, distinct partitioned register file structures in addition to the heterogeneous clustered datapath architecture to attain low power consumption and reduced die size; however, these architectural features lend new challenges to the compiler construction. This paper describes our employment of the Open Research Compiler (ORC) infrastructure on PAC DSP architectures and the specific compilation design. Preliminary results indicated that our compiler development for PAC DSP is effective for the architecture and the evaluation is useful for the refinement of the architecture. Our experiences in designing the compiler support for heterogeneous VLIW DSP processors with irregular resource constraints may benefit the similar architectures.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2006

Authors and Affiliations

  • Yung-Chia Lin
    • 1
  • Chung-Lin Tang
    • 1
  • Chung-Ju Wu
    • 1
  • Ming-Yu Hung
    • 1
  • Yi-Ping You
    • 1
  • Ya-Chiao Moo
    • 1
  • Sheng-Yuan Chen
    • 1
  • Jenq-Kuen Lee
    • 1
  1. 1.Department of Computer ScienceNational Tsing-Hua UniversityHsinchuTaiwan

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