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OpenMP on Multicore Architectures

  • Christian Terboven
  • Dieter an Mey
  • Samuel Sarholz
Part of the Lecture Notes in Computer Science book series (LNCS, volume 4935)

Abstract

Dualcore processors are already ubiquitous, quadcore processors will spread out this year, systems with a larger number of cores exist, and more are planned. Some cores even execute multiple threads. Are these processors just SMP systems on a chip? Is OpenMP ready to be used for these architectures? We take a look at the cache and memory architecture of some popular modern processors using kernel programs and some application codes which have been developed for large shared memory machines beforehand.

Keywords

Memory Bandwidth Cache Line Multicore Processor Memory Latency Multicore Architecture 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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References

  1. 1.
    Terboven, C., Spiegel, A., an Mey, D., Gross, S., Reichelt, V.: Parallelization of the C++ Navier-Stokes Solver DROPS with OpenMP. In: Proc. ParCo 2005, Malaga, Spain, September 2005. NIC book series, Research Centre Jülich, Germany, vol. 33 (2005)Google Scholar
  2. 2.
    Jerabkova, L., Terboven, C., Sarholz, S., Kuhlen, T., Bischof, C.: Exploiting Multicore Architectures for Physically Based Simulation of Deformable Objects in Virtual Environments. In: 4th workshop on Virtuelle und erweiterte Realität, Weimar, Germany (July 2007) (accepted)Google Scholar
  3. 3.
    an Mey, D., Haarmann, T.: Pushing Loop-Level Parallelization to the Limit. In: EWOMP 2002, Rome, Italy (September 2002)Google Scholar
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    Hörschler, I., Meinke, M., Schröder, W.: Numerical simulation of the flow field in a model of the nasal cavity. Computers & Fluids 32, 3945 (2003)CrossRefGoogle Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2008

Authors and Affiliations

  • Christian Terboven
    • 1
  • Dieter an Mey
    • 1
  • Samuel Sarholz
    • 1
  1. 1.Center for Computing and CommunicationRWTH Aachen University 

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