SL – A Structural Hardware Design Language
SL is a simple language designed to improve the productivity of hardware design. It is easy to use and it adopts reusable word-level and bit-level descriptions. This results in concise and easily grasped descriptions which give a good overview of the design. Used together with our SLAVE compiler, SL offers a fast way to produce complicated structural VHDL-code. This structural VHDL-code can then be used by Velab VHDL elaborator in order to produce a netlist for Xilinx XC6200 FPGA.
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