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A High Speed ATM/IP Switch Fabric Using Distributed Scheduler

  • Ali Mohammad Zareh Bidoki
  • Nasser Yazdani
  • Sayed Vahid Azhari
  • Siavash Samadian-Barzoki
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2662)

Abstract

An increasing number of high performance IP routers, LANs and Asynchronous Transfer Mode (ATM) switches use crossbar switches in their backplanes. Most of these systems use input queuing to store packets. Obviously, we will encounter Head of Line (HoL) blocking in input queues which decrease throughput to 56.8% under uniform traffic. In this paper, we develop a switch fabric with 16-input/output ports using crossbar architecture with internal partitioned memory in the feedback path. Our design also uses virtual output queuing (VOQ) with adaptive intelligent scheduling in each input port. The system distributes the scheduling algorithm to reach higher aggregated throughput. The switch fabric is internally non-blocking and avoids HoL by using VOQs. It is shown in the paper that its throughput and delay are very well compared to the current high performance switch fabrics. The architecture supports full Multicasting. By using bit-slicing the total capacity of the switch can be extended to 640 Gb/s. Distributed scheduling well maximizes the capacity and processing speed of the switch. Simulation results show that it is possible to reach 100% throughput with our design.

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References

  1. 1.
    Anderson, T., et al.: High speed switch scheduling for local area networks. ACM Trans. on Computer Systems, 319–352 (1993)Google Scholar
  2. 2.
    Andersson, P., et al.: A VLSI Architecture for an 80 Gb/s ATM Switch Core. In: Proc. 8th Annual IEEE Intl Conf. Innovative System in Silicon, Austin, TX, pp. 9–11 (1996)Google Scholar
  3. 3.
    Yoshigoe, K., et al.: A parallel- polled Virtual Output Queued Switch with a Buffered Crossbar (2001)Google Scholar
  4. 4.
    Del Re, E., et al.: Performance Evaluation of Input and Output Queueing Techniques in ATM Switching Systems. IEEE Trans. Commun. 41(10) (1993)Google Scholar
  5. 5.
    Karol, M., et al.: Input versus output queueing on a space division switch. IEEE Trans.Communications 35(12), 1347–1356 (1988)CrossRefGoogle Scholar
  6. 6.
    Katevenis, M., et al.: ATLAS I: A General-Purpose, Single-Chip ATM Switch with Credit-Based Flow Control. In: Proc. IEEE Hot Interconnects IV Symposium, Stanford, CA, pp. 15–17 (1996)Google Scholar
  7. 7.
    Kim, K., et al.: MASCON:A single IC solution to ATM Multi-Channel switching with Embedded Multicating. IEEE/ACM Trans. networking (1997)Google Scholar
  8. 8.
    Mckeown, N., Gupta, P.: Design and Implementation of a Fast Crossbar Scheduler (2000)Google Scholar
  9. 9.
    Mckeown, N.W.: Scheduling Algorithms for Input-Queued Switches, Ph.D. Thesis, University of California at Berkeley (1995)Google Scholar
  10. 10.
    Mckeown, N., Prabhakar, B.: Scheduling Multicast Cells in an Input-Queued Switch. In: Proc. INFOCOM 1996, San Francisco, CA, pp. 271–278 (1996)Google Scholar
  11. 11.
    Mckeown, N., et al.: The Tiny Tera: A Packet Switch Core, IEEE Micro Magazine (January-February 1997); Packet Switch Core Hot Interconnects V, Stanford University, pp. 26-33 (1996)Google Scholar
  12. 12.
    Mckeown, N.: The iSLIP Scheduling Algorithm for Input-Queued Switches. IEEE/ACM Trans. Networking 7(2), 188–201 (1999)Google Scholar
  13. 13.
    Minkenberg, C.J.A.: An Integrated Method for Unicast and Multicast Scheduling in a Combined Input and Output Buffered Packet Switching System, pending patent application CH, 8-1999-0098 (1999)Google Scholar
  14. 14.
    Partridge, C., et al.: A fifty gigabit per second IP router. To appear in IEEE/ACM Transactions on Networking (1998)Google Scholar
  15. 15.
    Sidiropoulos, S., et al.: Current Integrating Receivers for High Speed System Interconnects. In: IEEE Custom Integrated Circuits Conference (1995)Google Scholar
  16. 16.
    Tamir, Y., Frazier, G.L.: Dynamically Allocated Multi-Queue Buffers for VLSI ommunication Switches. IEEE Trans. Computers 41(6), 725–737 (1992)CrossRefGoogle Scholar
  17. 17.
    Turner, J.S.: Terabit Burst Switching, Washington University Technical Report, WUCS-98-17 (1998)Google Scholar
  18. 18.
    Virtex-II Pro data sheet, http://www.xilinx.com
  19. 19.
    Tobagi, F.: Fast Packet Switch Architectures for Braodband Integrated Services Digital Networks. Proc. IEEE 78(1), 133–167 (1990)CrossRefGoogle Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2003

Authors and Affiliations

  • Ali Mohammad Zareh Bidoki
    • 1
  • Nasser Yazdani
    • 1
  • Sayed Vahid Azhari
    • 1
  • Siavash Samadian-Barzoki
    • 1
  1. 1.Router Lab., ECE. Dept., Faculty of EngineeringUniv. of TehranTehranIran

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