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Design Flow for Efficient FPGA Reconfiguration

  • Richard H. Turner
  • Roger F. Woods
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2778)

Abstract

In Run Time Reconfiguration (RTR) systems, the amount of reconfiguration is considerable when compared to the circuit changes implemented. This is because reconfiguration is not considered as part of the design flow. This paper presents a method for reconfigurable circuit design by modeling the underlying FPGA reconfigurable circuitry and taking it into consideration in the system design. This is demonstrated for an image processing example on the Xilinx Virtex FPGA.

Keywords

Design Flow Configuration Data Adaptive Signal Processing Reconfiguration Time Polyphase Filter 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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References

  1. 1.
    Turner, R.H.: Functionally Diverse Programmable Logic Implementations of Digital Signal Processing Algorithms, PhD Diss., Queen’s University Belfast (2002)Google Scholar
  2. 2.
    Ang, C.N., Turner, R.H., Courtney, T., Woods, R.: Virtex FPGA Implementation of a Polyphase Filter for Sample Rate Conversion. In: 34th Asilomar Conf. on Signals, Syst. and Comp., USA, pp. 365–369. IEEE Comp. Soc., Los Alamitos (2000)Google Scholar
  3. 3.
    Courtney, T., Turner, R.H., Woods, R.: An Investigation of Reconfigurable Multipliers for use in Adaptive Signal Processing. In: IEEE Symp. on FCCM, Napa, USA, May 2000, pp. 341–343 (2000)Google Scholar
  4. 4.
    Shirazi, N., Luk, W., Cheung, P.: Automating Production of Run-Time Reconfigurable Designs. In: Proc. IEEE Symp. on FCCM, USA, pp. 147–156 (1998)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2003

Authors and Affiliations

  • Richard H. Turner
    • 1
  • Roger F. Woods
    • 1
  1. 1.Programmable Systems LaboratoryQueen’s University BelfastBelfastNorthern Ireland

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