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Arbitrating Instructions in an ρμ-Coded CCM

  • Georgi Kuzmanov
  • Stamatis Vassiliadis
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2778)

Abstract

In this paper, the design aspects of instruction arbitration in an ρμ-coded CCM are discussed. Software considerations, architectural solutions, implementation issues and functional testing of an ρμ-code arbiter are presented. A complete design of such an arbiter is proposed and its VHDL code is synthesized for the VirtexII Pro platform FPGA of Xilinx. The functionality of the unit is verified by simulations. A very low utilization of available reconfigurable resources is achieved after the design is synthesized. Simulations of an MPEG-4 case study suggest considerable performance speed-up in the range of 2,4-8,8 versus a pure software PowerPC implementation.

Keywords

Link Register Core Processor Wait State Branch Instruction Architectural Solution 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2003

Authors and Affiliations

  • Georgi Kuzmanov
    • 1
  • Stamatis Vassiliadis
    • 1
  1. 1.Computer Engineering Lab, Electrical Engineering Dept.EEMCS, TU DelftThe Netherlands

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