Compiling for the Molen Programming Paradigm

  • Elena Moscu Panainte
  • Koen Bertels
  • Stamatis Vassiliadis
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2778)


In this paper we present compiler extensions for the Molen programming paradigm, which is a sequential consistency paradigm for programming custom computing machines (CCM). The compiler supports instruction set extensions and register file extensions. Based on pragma annotations in the application code, it identifies the code fragments implemented on the reconfigurable hardware and automatically maps the application on the target reconfigurable architecture. We also define and implement a mechanism that allows multiple operations to be executed in parallel on the reconfigurable hardware. In a case study, the Molen processor has been evaluated. We considered two popular multimedia benchmarks: mpeg2enc and ijpeg and some well-known time-consuming operations implemented in the reconfigurable hardware. The total number of executed instructions has been reduced with 72% for mpeg2enc and 35% for ijpeg encoder, compared to their pure software implementations on a general purpose processor (GPP).


Hardware Implementation Parallel Execution Register File Programming Paradigm Register Allocation 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.


  1. 1.
    Sima, M., Vassiliadis, S., Cotofana, S., van Eijndhoven, J., Vissers, K.: Field-Programmable Custom Computing Machines – A Taxonomy. In: Glesner, M., Zipf, P., Renovell, M. (eds.) FPL 2002. LNCS, vol. 2438, pp. 79–88. Springer, Heidelberg (2002)Google Scholar
  2. 2.
    Gokhale, M., Stone, J.: Napa C: Compiling for a Hybrid RISC/FPGA Architecture. In: Proc. IEEE Symp. on Field-Programmable Custom Computing Machines, Napa, California, April 1998, pp. 126–137 (1998)Google Scholar
  3. 3.
    Hauck, S., Fry, T.W., Hosler, M.M., Kao, J.P.: The Chimaera Reconfigurable Functional Unit. In: Proc. IEEE Symp. on Field-Programmable Custom Computing Machines, Napa, California, pp. 87–96 (1997)Google Scholar
  4. 4.
    Rosa, A.L., Lavagno, L., Passerone, C.: Hardware/Software Design Space Exploration for a Reconfigurable Processor. In: Proc. of the DATE 2003, pp. 570–575 (2003)Google Scholar
  5. 5.
    Campi, F., Canegallo, R., Guerrieri, R.: IP-Reusable 32-Bit VLIW Risc Core. In: Proc. of the 27th European Solid-State Circuits Conference, Villah, Austria, September 2001, pp. 456–459 (2001)Google Scholar
  6. 6.
    Ye, Z., Shenoy, N., Banerjee, P.: A C Compiler for a Processor with a Reconfigurable Functional Unit. In: ACM/SIGDA Symposium on FPGAs, Montery, California, USA, pp. 95–100 (2000)Google Scholar
  7. 7.
    Vassiliadis, S., Wong, S., Cotofana, S.: The MOLEN ρμ-Coded Processor. In: Brebner, G., Woods, R. (eds.) FPL 2001. LNCS, vol. 2147, pp. 275–285. Springer, Heidelberg (2001)CrossRefGoogle Scholar
  8. 8.
  9. 9.
  10. 10.
    Mercaldi, M., Smith, M.D., Holloway, G.: The Halt Library. In: The Machine- SUIF Documentation Set. Hardvard University, Cambridge (2002)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2003

Authors and Affiliations

  • Elena Moscu Panainte
    • 1
  • Koen Bertels
    • 1
  • Stamatis Vassiliadis
    • 1
  1. 1.Computer Engineering Lab, Electrical Engineering DepartmentTU DelftThe Netherlands

Personalised recommendations