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Switch Level Fault Emulation

  • Seyed Ghassem Miremadi
  • Alireza Ejlali
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2778)

Abstract

The switch level is an abstraction level between the gate level and the electrical level, offers many advantages. Switch level simulators can reliably model many important phenomena in CMOS circuits, such as bi-directional signal propagation, charge sharing and variations in driving strength. However, the fault simulation of switch level models is more time-consuming than gate level models. This paper presents a method for fast fault emulation of switch level circuits using FPGA chips. In this method, gates model switch level circuits and we can emulate mixed gate-switch level models. By the use of this method, FPGA chips can be used to accelerate the fault injection campaigns into switch level models.

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References

  1. 1.
    Varghese, J., Butts, M., Batcheller, J.: An efficient logic emulation system. IEEE Trans. VLSI Syst. 1, 171–174 (1993)CrossRefGoogle Scholar
  2. 2.
    Walters, S.: Computer-aided prototyping for ASIC-based system. IEEE Design Test Comput., 4–10 ( June 1991)Google Scholar
  3. 3.
    Khan, U.R., Owen, H.L., Hughes, J.L.: FPGA Architecture for ASIC Hardware Emulator. In: Proc. 6, IEEE ASIC Conference, p. 336 (1993)Google Scholar
  4. 4.
    Cheng, K.T., Huang, S.Y., Dai, W.J.: Fault Emulation: A New Methodology for Fault Grading. IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems 18(10), 1487–1495 (1999)CrossRefGoogle Scholar
  5. 5.
    Dahlgren, P., Liden, P.: Efficient Modeling of Switch-Level Networks Containing Undetermined Logic Node States. In: Proc. IEEE/ACM Int. Conf. on CAD, pp. 746–752 (1993)Google Scholar
  6. 6.
    Bryant, R.E.: A Switch-Level Model and Simulator for MOS Digital Systems. IEEE Trans. Computers C-33(2), 160–177 (1984)MathSciNetCrossRefGoogle Scholar
  7. 7.
    Abramovici, M., Breuer, M.A., Friedman, A.D.: Digital Systems Testing and Testable Design. IEEE Press, Los Alamitos (1995) (revised edition)Google Scholar
  8. 8.
    Verilog Hardware Descriptor Language Reference Manual (LRM) DRAFT. IEEE 1364 (April 1995)Google Scholar
  9. 9.
    Choi, G.S., Iyer, R.K.: FOCUS: An Experimental Environment for Fault Sensitivity Analysis. IEEE Trans. Computers 41(12), 1515–1526 (1992)CrossRefGoogle Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2003

Authors and Affiliations

  • Seyed Ghassem Miremadi
    • 1
  • Alireza Ejlali
    • 1
  1. 1.Department of Computer EngineeringSharif University of TechnologyTehranIran

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