Evaluation of Testability of Path Delay Faults for User-Configured Programmable Devices

  • Andrzej Krasniewski
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2778)


A model of the combinational section of a programmable device suitable for an analysis of testability of delay faults is proposed. All relevant factors that affect the evaluation of testability of path delay faults are identified and their impact on the outcome of the evaluation is discussed. A detailed analysis, supported by quantitative results, focuses on the selection of the set of target faults in terms of a class of logical paths and on the concept of defining testability measures for physical paths rather than for logical paths. Practical guidelines are formulated for the development of a procedure for the evaluation of testability of path delay faults.


Critical Path Testability Measure Fault Coverage Programmable Device Delay Fault 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.


  1. 1.
    Krstic, A., Liou, J.-J.: Delay Testing Considering Crosstalk-Induced Effects. In: Proc. IEEE Int. Test Conf., pp. 558-567 (2001)Google Scholar
  2. 2.
    Metra, C., Pagano, A., Ricco, B.: On-Line Testing of Transient and Crosstalk Faults Affecting Interconnections of FPGA-Implemented Systems. In: Proc. IEEE Int. Test Conf., pp. 939-947 (2001)Google Scholar
  3. 3.
    Abramovici, M., Stroud, C.: BIST-Based Delay-Fault Testing in FPGAs. In: Proc. IEEE Int. On-Line Testing Workshop (2002)Google Scholar
  4. 4.
    Renovell, M., Faure, P., Portal, J.M., Figueras, J., Zorian, Y.: IS-FPGA: A New Symmetric FPGA Architecture with Implicit SCAN. In: Proc. IEEE Int. Test Conf., pp. 924-931 (2001)Google Scholar
  5. 5.
    Krasniewski, A.: Application-Dependent Testing of FPGA Delay Faults. In: Proc. 25th EUROMICRO Conf., vol. 1, pp. 260-267 (1999)Google Scholar
  6. 6.
    Stroud, C., Konala, S., Chen, P., Abramovici, M.: Built-In Self-Test of Logic Blocks in FPGAs (Finally, a Free Lunch: BIST Without Overhead!). In: Proc. 14th VLSI Test Symp., pp. 387-392 (1996)Google Scholar
  7. 7.
    Harris, I.G., Menon, P.R., Tessier, R.: BIST-Based Delay Path Testing in FPGA Architectures. In: Proc. IEEE Int. Test Conf., pp. 932-938 (2001)Google Scholar
  8. 8.
    Krasniewski, A.: Testing FPGA Delay Faults: It Is Much More Complicated Than It Appears. In: Ciazynski, W., et al. (eds.) Programmable Devices and Systems, pp. 281–286. Pergamon - Elsevier Science (2002)Google Scholar
  9. 9.
    Sparmann, U., et al.: Fast Identification of Robust Dependent Path Delay Faults. In: Proc. 32nd ACM/IEEE Design Automation Conf., pp. 119-125 (1995)Google Scholar
  10. 10.
    Cheng, K.-T., Chen, H.-C.: Classification and Identification of Nonrobust Untestable Path Delay Faults. IEEE Trans. on CAD 8, 845–853 (1996)CrossRefGoogle Scholar
  11. 11.
    Krstic, A., Cheng, K.-T., Chakradhar, S.T.: Primitive Delay Faults: Identification, Testing, and Design for Testability. IEEE Trans. on CAD 11, 669–684 (1999)CrossRefGoogle Scholar
  12. 12.
    Krasniewski, A.: Sensitization of Logical Paths in a Network of Arbitrary Logic Components: Theory and Application to Delay Fault Testing. In: Proc. IEEE Design and Diagnostics of Electronics Circuits and Systems Workshop, pp. 143-150 (2003)Google Scholar
  13. 13.
    Krasniewski, A.: On the Set of Target Path Delay Faults in Sequential Subcircuits of LUTBased FPGAs. In: Glesner, M., Zipf, P., Renovell, M. (eds.) FPL 2002. LNCS, vol. 2438, pp. 616–626. Springer, Heidelberg (2002)CrossRefGoogle Scholar
  14. 14.
    Underwood, B., Law, W.-O., Kang, S., Konuk, H.: Fastpath: A Path-Delay Test Generator for Standard Scan Designs. In: Proc. IEEE Int’l Test Conf., pp. 154-163 (1994)Google Scholar
  15. 15.
    Majhi, A.K., Agrawal, V.D., Jacob, J., Patnaik, L.M.: Line Coverage of Path Delay Faults. IEEE Trans. on VLSI Systems 8, 610–613 (2000)CrossRefGoogle Scholar
  16. 16.
    Krasniewski, A.: Evaluation of the Quality of Testing Path Delay Faults Under Restricted Input Assumption. In: Proc. IEEE Int. On-Line Testing Symp. (2003) (in printing)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2003

Authors and Affiliations

  • Andrzej Krasniewski
    • 1
  1. 1.Institute of TelecommunicationsWarsaw University of TechnologyWarsawPoland

Personalised recommendations