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Evaluation of Testability of Path Delay Faults for User-Configured Programmable Devices

  • Andrzej Krasniewski
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2778)

Abstract

A model of the combinational section of a programmable device suitable for an analysis of testability of delay faults is proposed. All relevant factors that affect the evaluation of testability of path delay faults are identified and their impact on the outcome of the evaluation is discussed. A detailed analysis, supported by quantitative results, focuses on the selection of the set of target faults in terms of a class of logical paths and on the concept of defining testability measures for physical paths rather than for logical paths. Practical guidelines are formulated for the development of a procedure for the evaluation of testability of path delay faults.

Keywords

Critical Path Testability Measure Fault Coverage Programmable Device Delay Fault 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2003

Authors and Affiliations

  • Andrzej Krasniewski
    • 1
  1. 1.Institute of TelecommunicationsWarsaw University of TechnologyWarsawPoland

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