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A Modular Reconfigurable Architecture for Efficient Fault Simulation in Digital Circuits

  • J. Soares Augusto
  • C. Beltrán Almeida
  • H. C. Campos Neto
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2778)

Abstract

In this paper, a modular reconfigurable architecture for efficient stuck-at fault simulation in digital circuits is described. The architecture is based on a Universal Faulty Gate Block, which models each 2-input gate by a 4-input Look-Up Table (LUT) and a Shift-Register (SR) with 3 stages, and relies on collapsing the stuck-at fault list of the gates using equivalence and dominance relations between faults. An example is presented, the expected performance is estimated and the applicability and limitations of the architecture are discussed.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2003

Authors and Affiliations

  • J. Soares Augusto
    • 1
  • C. Beltrán Almeida
    • 1
  • H. C. Campos Neto
    • 1
  1. 1.INESC/ISTLisboaPortugal

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