A Dual-Path Logarithmic Number System Addition/Subtraction Scheme for FPGA

  • Barry Lee
  • Neil Burgess
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2778)


A new architecture for calculating the addition/subtraction function required in a logarithmic number system (LNS) is presented. A substantial logic saving over previous works is illustrated along with similarities with the dual-path floating-point addition method. The new architecture constrains the lookups to be of fractional width and uses shifting to achieve this. Instead of calculating the function \(\log_2(1\pm2^{M-K})\) in two lookups the function arithmetic is performed (i.e. the two functions 2M −  K and log2( ), plus a correction function) as this allows logic sharing that maps well to FPGA. Better-than-floating-point (BTFP) accuracy is used to enable a future comparison with floating-point.


Addition Function Correction Function FPGA Implementation Fractional Width Hardware Model 
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Copyright information

© Springer-Verlag Berlin Heidelberg 2003

Authors and Affiliations

  • Barry Lee
    • 1
  • Neil Burgess
    • 1
  1. 1.Cardiff school of EngineeringCardiff UniversityCardiffUK

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