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A Dual-Path Logarithmic Number System Addition/Subtraction Scheme for FPGA

  • Barry Lee
  • Neil Burgess
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2778)

Abstract

A new architecture for calculating the addition/subtraction function required in a logarithmic number system (LNS) is presented. A substantial logic saving over previous works is illustrated along with similarities with the dual-path floating-point addition method. The new architecture constrains the lookups to be of fractional width and uses shifting to achieve this. Instead of calculating the function \(\log_2(1\pm2^{M-K})\) in two lookups the function arithmetic is performed (i.e. the two functions 2M −  K and log2( ), plus a correction function) as this allows logic sharing that maps well to FPGA. Better-than-floating-point (BTFP) accuracy is used to enable a future comparison with floating-point.

Keywords

Addition Function Correction Function FPGA Implementation Fractional Width Hardware Model 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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References

  1. 1.
    Lewis, D.M.: Interleaved Memory Function Interpolators with Application to an Accurate LNS Arithmetic Unit. IEEE Trans. on Comp. 974–982 (August 1994)Google Scholar
  2. 2.
    Arnold, M.G., Walter, C.: Unrestricted Faithful Rounding is Good Enough for Some LNS Applications. In: 15th symp. on Comp. Arith. pp. 237–246 (2001)Google Scholar
  3. 3.
    Chen, C., Chen, R., Yang, C.: Pipelined Computation of Very Large Word-length LNS Addition/Subtraction with Polynomial Hardware Cost. IEEE Trans. on Comp. 716–726 (July 2000)Google Scholar
  4. 4.
    Poliouris, V., Stouraitis, T.: A Novel Algorithm for Accurate Logarithmic Number System Subtraction. In: IEEE Symp. on Circuits and Sys. pp. 268–271 (May 1996)Google Scholar
  5. 5.
    IEEE Standard for Binary Floating-Point Arithmetic. ANSI/IEEE std. 754 (1985)Google Scholar
  6. 6.
    Lee, B.R., Burgess, N.: Parameterisable Floating-Point operations on FPGA. In: 36th Asilomar Conf. on Signals, Systems and Comp. (November 2002)Google Scholar
  7. 7.
    Taylor, F.J., Gill, R., Joseph, J., Radke, J.: A 20-bit Logarithmic Number System Processor. IEEE Trans. on Comps. 190–199 (February 1988)Google Scholar
  8. 8.
    Matousek, R., Tichy, M., Pohl, M., Kadlec, J., Softley, C., Coleman, N.: Logarithmic Number System and Floating-Point Arithmetics on FPGA. In: Glesner, M., Zipf, P., Renovell, M. (eds.) FPL 2002. LNCS, vol. 2438, pp. 626–636. Springer, Heidelberg (2002)CrossRefGoogle Scholar
  9. 9.
    Schulte, M.J., Swartzlander Jr., E.E.: Hardware Designs for Exactly Rounded Elementary Functions. IEEE Trans. on Comp. 964–973 (August 1994)Google Scholar
  10. 10.
    Xilinx. Virtex-II Platform FPGA Handbook (December 2000)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2003

Authors and Affiliations

  • Barry Lee
    • 1
  • Neil Burgess
    • 1
  1. 1.Cardiff school of EngineeringCardiff UniversityCardiffUK

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