Advertisement

A Generic Architecture for Integrated Smart Transducers

  • Martin Delvai
  • Ulrike Eisenmann
  • Wilfried Elmenreich
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2778)

Abstract

A smart transducer network hosts various nodes with different functionality. Our approach offers the possibility to design different smart transducer nodes as a system-on-a-chip within the same platform. Key elements are a set of code compatible processor cores which can be equipped with several extension modules. Due to the fact that all processor cores are code compatible, programs developed for one node run on all other nodes without any modification. A well-defined interface between processor cores and extension modules ensures that all modules can be used with every processor type. The applicability of the proposed approach is shown by presenting our experiences with the implementation of a smart transducer featuring the processor core and a UART extension module on an FPGA.

Keywords

Clock Cycle Processor Core Controller Area Network Communication Interface Extension Module 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. 1.
    Elmenreich, W., Pitzek, S.: Smart transducers – principles, communications, and configuration. In: Proceedings of the 7th IEEE International Conference on Intelligent Engineering Systems (INES 2003), Assuit – Luxor, Egypt, March 2003, vol. 2, pp. 510–515 (2003)Google Scholar
  2. 2.
    Dierauer, P., Woolever, B.: Understanding smart devices. In: Industrial Computing, pp. 47–50 (1998)Google Scholar
  3. 3.
    Delvai, M., Eisenmann, U., Huber, W.: Modular construction system for embedded real-time applications. In: Tagungsband of Austrochip 2002, Vienna, Austria (2002)Google Scholar
  4. 4.
    Puschner, P., Burns, A.: A review of worst-case execution-time analysis. Journal of Real-Time Systems 18(2/3), 115–128 (2000)CrossRefGoogle Scholar
  5. 5.
    Poledna, S., Angelow, H., Glück, M., Pisecky, M., Smaili, I., Stöger, G., Tanzer, C., Kroiss, G.: TTP two level design approach: Tool support for composable faulttolerant real-time systems. In: SAE World Congress 2000, Detroit, MI, USA (March 2000)Google Scholar
  6. 6.
    Object Management Group (OMG): Smart Transducers Interface Final Adopted Specification as document ptc/2002-10-02 (August 2002), Available at http://www.omg.org
  7. 7.
    Kopetz, H., Nossal, R.: Temporal firewalls in large distributed real-time systems. In: Proceedings of the 6th IEEE Workshop on Future Trends of Distributed Computing Systems (FTDCS 1997), pp. 310–315 (1997)Google Scholar
  8. 8.
    Delvai, M., Huber, W., Puschner, P., Steininger, A.: Processor support for temporal predictability - The SPEAR design example. In: Proceedings of the 15th Euromicro Conference on Real-Time Systems, Porto, Portugal (July 2003)Google Scholar
  9. 9.
    Elmenreich, W., Delvai, M.: Time-triggered communication with UARTs. In: Proceedings of the 4th IEEE International Workshop on Factory Communication Systems (WFCS 2002), Västerås, Sweden (August 2002)Google Scholar
  10. 10.
    Kopetz, H., et al.: Specification of the TTP/A protocol. Technical report, Technische Universität Wien, Institut für Technische Informatik, Vienna, Austria (March 2000), Available at http://www.ttpforum.org
  11. 11.
    Audi, A.G., DaimlerChrysler, B.A., Motorola Inc, A.G.: Volcano Communication Technologies AB, Volkswagen AG, and Volvo Car Corporation. LIN specification and LIN press announcement. In: SAE World Congress Detroit (1999), http://www.linsubbus.org
  12. 12.
    Delvai, M., Jankela, M., Steininger, A.: Towards virtual prototyping of embedded computer systems. In: Proceedings of the 7th World Multiconference on Systemics, Cybernetics and Informatics (SCI 2003), Orlando, FL, USA (July 2003)Google Scholar
  13. 13.
    Delvai, M., El Salloum, C., Steininger, A.: A generic real-time debugger architecture. In: Proceedings of the 7th World Multiconference on Systemics, Cybernetics and Informatics (SCI 2003), Orlando, FL, USA (July 2003)Google Scholar
  14. 14.
    Gupta, R.K., Zorian, Y.: Introducing core-based system design. IEEE Design & Test of Computers 14(4), 15–25 (1997)CrossRefGoogle Scholar
  15. 15.
    Licznerski, B.W., Nitsch, K., Teterycz, H.: Polycrystalline wide bandgap materials in sensor technology. In: Abstract Book of the 3rd International Conference on Novel Applications of Wide Bandgap Layers, pp. 32–35, Poland (2001)Google Scholar
  16. 16.
    Vaezi-Nejad, S.M.: Advanced sensors scene in europe. In: Proceedings of the IEEE Instrumentation and Measurement Technology Conference, Ottawa, Canada, May 1997, vol. 2, pp. 926–931 (1997)Google Scholar
  17. 17.
    Fedder, G.K.: Structured design of integrated MEMS. In: Proceedings of the 12th IEEE International Conference on Micro Electro Mechanical Systems, pp. 1–8 (January 1999)Google Scholar
  18. 18.
    Institute of Electrical and Electronics Engineers, Inc. IEEE Std 1451.2-1997, Standard for a Smart Transducer Interface for Sensors and Actuators - Transducer to Micro-processor Communication Protocols and Transducer Electronic Data Sheet (TEDS) Formats (September 1997)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2003

Authors and Affiliations

  • Martin Delvai
    • 1
  • Ulrike Eisenmann
    • 1
  • Wilfried Elmenreich
    • 1
  1. 1.Institut für Technische InformatikUniversity of TechnologyViennaAustria

Personalised recommendations