A Generic Architecture for Integrated Smart Transducers

  • Martin Delvai
  • Ulrike Eisenmann
  • Wilfried Elmenreich
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2778)


A smart transducer network hosts various nodes with different functionality. Our approach offers the possibility to design different smart transducer nodes as a system-on-a-chip within the same platform. Key elements are a set of code compatible processor cores which can be equipped with several extension modules. Due to the fact that all processor cores are code compatible, programs developed for one node run on all other nodes without any modification. A well-defined interface between processor cores and extension modules ensures that all modules can be used with every processor type. The applicability of the proposed approach is shown by presenting our experiences with the implementation of a smart transducer featuring the processor core and a UART extension module on an FPGA.


Clock Cycle Processor Core Controller Area Network Communication Interface Extension Module 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Springer-Verlag Berlin Heidelberg 2003

Authors and Affiliations

  • Martin Delvai
    • 1
  • Ulrike Eisenmann
    • 1
  • Wilfried Elmenreich
    • 1
  1. 1.Institut für Technische InformatikUniversity of TechnologyViennaAustria

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