A New Arithmetic Unit in GF(2m) for Reconfigurable Hardware Implementation

  • Chang Hoon Kim
  • Soonhak Kwon
  • Jong Jin Kim
  • Chun Pyo Hong
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2778)


This paper proposes a new arithmetic unit (AU) in GF(2m) for reconfigurable hardware implementation such as FPGAs, which overcomes the well-known drawback of reduced flexibility that is associated with traditional ASIC solutions. The proposed AU performs both division and multiplication in GF(2m). These operations are at the heart of elliptic curve cryptosystems (ECC). Analysis shows that the proposed AU has significantly less area complexity and has roughly the same or lower latency compared with some related circuits. In addition, we show that the proposed architecture preserves a high clock rate for large m (up to 571), when it is implemented on Altera’s EP2A70F1508C-7 FPGA device. Furthermore, the new architecture provides a high flexibility and scalability with respect to the field size m, since it does not restrict the choice of irreducible polynomials and has the features of regularity, modularity, and unidirectional data flow. Therefore, the proposed architecture is well suited for both division and multiplication unit of ECC implemented on FPGAs.


Finite Field Division Finite Field Multiplication ECC VLSI 


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.


  1. 1.
    Blake, I.F., Seroussi, G., Smart, N.P.: Elliptic Curves in Cryptography. Cambridge University Press, Cambridge (1999)CrossRefGoogle Scholar
  2. 2.
    Orlando, G., Parr, C.: A High-Performance Reconfigurable Elliptic Curve Processor for GF(2m). In: Paar, C., Koç, Ç.K. (eds.) CHES 2000. LNCS, vol. 1965, p. 41. Springer, Heidelberg (2000)CrossRefGoogle Scholar
  3. 3.
    Bednara, M., Daldrup, M., von zur Gathen, J., Shokrollahi, J., Teich, J.: Reconfigurable Implementation of Elliptic Curve Crypto Algorithms. In: Proc. of the International Parallel and Distributed Processing Symposium (IPDPS 2002), pp. 157–164 (2002)Google Scholar
  4. 4.
    Wang, C.-L., Lin, J.-L.: A Systolic Architecture for Computing Inverses and Divisions in Finite Fields GF(2m). IEEE Trans. Computers 42(9), 1141–1146 (1993)MathSciNetCrossRefGoogle Scholar
  5. 5.
    Hasan, M.A., Bhargava, V.K.: Bit-Level Systolic Divider and Multiplier for Finite Fields GF(2m). IEEE Trans. Computers 41(8), 972–980 (1992)MathSciNetCrossRefGoogle Scholar
  6. 6.
    Guo, J.-H., Wang, C.-L.: Systolic Array Implementation of Euclid’s Algorithm for Inversion and Division in GF(2m). IEEE Trans. Computers 47(10), 1161–1167 (1998)CrossRefGoogle Scholar
  7. 7.
    Goodman, J.R.: Energy Scalable Reconfigurable Cryptographic Hardware for Portable Applications. PhD thesis, MIT (2000)Google Scholar
  8. 8.
    Guo, J.-H., Wang, C.-L.: Bit-serial Systolic Array Implementation of Euclid’s Algorithm for Inversion and Division in GF(2m). In: Proc. 1997 Int. Symp. VLSI Tech., Systems and Applications, pp. 113–117 (1997)Google Scholar
  9. 9.
    Wang, C.L., Lin, J.L.: Systolic Array Implementation of Multipliers for Finite Field GF(2m). IEEE Trans. Circuits and Syst. 38(7), 796–800 (1991)CrossRefGoogle Scholar
  10. 10.
    Blum, T., Paar, C.: High Radix Montgomery Modular Exponentiation on Reconfigurable Hardware. IEEE Trans. Computers 50(7), 759–764 (2001)CrossRefGoogle Scholar
  11. 11.
    Han, S.D., Kim, C.H., Hong, C.P.: Characteristic Analysis of Modular Multiplier for GF(2m). In: Proc. of IEEK Summer Conference 2002, vol. 25(1), pp. 277–280 (2002)Google Scholar
  12. 12.
    Tessier, R., Burleson, W.: Reconfigurable Computing for Digital Signal Processing: A Survey. J. VLSI Signal Processing 28(1), 7–27 (1998)zbMATHGoogle Scholar
  13. 13.
    Compton, K., Hauck, S.: Reconfigurable Computing: A Survey of Systems and Software. ACM Computing Surveys 34(2), 171–210 (2002)CrossRefGoogle Scholar
  14. 14.
    Kung, S.Y.: VLSI Array Processors. Prentice Hall, Englewood Cliffs (1988)Google Scholar
  15. 15.
    NIST, Recommended elliptic curves for federal government use (May 1999),
  16. 16.
    Altera, APEXTMII Programable Logic Device Family Data Sheet (August 2000),
  17. 17.
    Kim, C.H., Hong, C.P.: High Speed Division Architecture for GF(2m). Electronics Letters 38(15), 835–836 (2002)CrossRefGoogle Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2003

Authors and Affiliations

  • Chang Hoon Kim
    • 1
  • Soonhak Kwon
    • 2
  • Jong Jin Kim
    • 1
  • Chun Pyo Hong
    • 1
  1. 1.Dept. of Computer and Information EngineeringDaegu UniversityJinryang, KyungsanKorea
  2. 2.Dept. of Mathematics and Inst. of Basic ScienceSungkyunkwan UniversitySuwonKorea

Personalised recommendations