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Implementation of HW$im – A Real-Time Configurable Cache Simulator

  • Shih-Lien Lu
  • Konrad Lai
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2778)

Abstract

In this paper, we describe a computer cache memory simulation environment based on a custom board with multiple FPGAs and DRAM DIMMs. This simulation environment is used for future memory hierarchy evaluation of either single or multiple processors systems. With this environment, we are able to perform real-time memory hierarchy studies running real applications. The board contains five Xilinx’ VirtexTM, II-1000 FPGAs and eight SDRAM DIMMs. One of the FPGA is used to interface with a microprocessor system bus. The other four FPGAs work in parallel to simulate different cache configurations. Each of these four FPGAs interfaces with two SDRAM DIMMs that are used to store the simulated cache. This simulation environment is operational and achieves a system frequency of 133MHz.

Keywords

Cache Size Memory Hierarchy Large Vocabulary Continuous Speech Recognition Clock Domain Field Programmable Gate Array Device 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2003

Authors and Affiliations

  • Shih-Lien Lu
    • 1
  • Konrad Lai
    • 1
  1. 1.Microprocessor ResearchIntel LabsHillsboroUSA

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