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An FPGA System for the High Speed Extraction, Normalization and Classification of Moment Descriptors

  • Stavros Paschalakis
  • Peter Lee
  • Miroslaw Bober
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2778)

Abstract

We propose a new FPGA system for the high speed extraction, normalization and classification of moment descriptors. Moments are extensively used in computer vision, most recently in the MPEG-7 standard for the region shape descriptor. The computational complexity of such methods has been partially addressed by the proposal of custom hardware architectures for the fast computation of moments. However, a complete system for the extraction, normalization and classification of moment descriptors has not yet been suggested. Our system is a hybrid, relying partly on a very fast parallel processing structure and partly on a custom built, low cost, reprogrammable processing unit. Within the latter, we also propose FPGA circuits for low cost double precision floating-point arithmetic. Our system achieves the extraction and classification of invariant descriptors for hundreds or even thousands of intensity or color images per second and is ideal for high speed and/or volume applications.

Keywords

Clock Cycle Double Precision Gate Count Invariant Descriptor Moment Descriptor 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2003

Authors and Affiliations

  • Stavros Paschalakis
    • 1
  • Peter Lee
    • 2
  • Miroslaw Bober
    • 1
  1. 1.Mitsubishi Electric ITE-VILThe Surrey Research ParkGuildfordUK
  2. 2.Department of ElectronicsUniversity of Kent at CanterburyCanterburyUK

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