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Fully Parameterized Discrete Wavelet Packet Transform Architecture Oriented to FPGA

  • Guillermo Payá
  • Marcos M. Peiró
  • Francisco Ballester
  • Francisco Mora
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2778)

Abstract

The present paper describes a fully parameterized Discrete Wavelet Packet Transform (DWPT) architecture based on a folded Distributed Arithmetic implementation, which makes possible to design any kind of wavelet bases. The proposed parameterized architecture allows different CDF wavelet coefficient with variable bit precision (data input and output size, and coefficient length). Moreover, by combining different blocks in cascade, we can expand as many complete stages (wavelet packet levels) as we require. Our architecture need only two FIR filters to calculate various wavelet stages simultaneously, and specific VIRTEX family resources (SRL16E) have been instantiated to reduce area and increase frequency operation. Finally, a DWPT implementation for CDF(9,7) wavelet coefficients is synthesized on VIRTEX-II 3000-6 FPGA for different precisions.

Keywords

Discrete Wavelet Transform Wavelet Packet Wavelet Packet Transform Quadrature Mirror Filter Distribute Arithmetic 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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References

  1. 1.
    Trenas, M. A., Lopez, J., Hongyi, C.: A Configurable Architecture for the Wavelet Packet Transform. IEE Electron Letters, 499–500 (1999)Google Scholar
  2. 2.
    Hilton, M.L.: Wavelet and Wavelet Packet Compression of Electrocardiograms. Technical Report TR9505, Department of Computer Science, University of South Carolina (1997)Google Scholar
  3. 3.
    Jamin, A., Mähönen, P.: FPGA Implementation of the Wavelet Packet Transform for High Speed Communications. In: Glesner, M., Zipf, P., Renovell, M. (eds.) FPL 2002. LNCS, vol. 2438, p. 212. Springer, Heidelberg (2002)CrossRefGoogle Scholar
  4. 4.
    Coifman, R., Meyer, Y., Quake, S., Wickerhauser, V.: Signal Processing an Compression with Wave Packets. Numerical Algorithms Research Group, Yale University (1990)Google Scholar
  5. 5.
    Croiser, A., Esteban, D.J., Levilion, M.E., Rizo, V.: Digital Filter for PCM Encoded Signals. U.S. Patent 3 777 130 (1973)Google Scholar
  6. 6.
    Peled, A., Liu, B.: A New Approach to the Realization of NonRecursive Digital Filter. IEEE Trans. On Audio and Electroacoustic 21(6), 477–485 (1973)CrossRefGoogle Scholar
  7. 7.
    LB_2DFDWT – Line-Based Programmable Forward DWT, AllianceCoreTM (2001) Google Scholar
  8. 8.
    White, S.A.: Applications of Distributed Arithmetic to Digital Signal Processing: a Tutorial Review. ASSP Magazine 6(3), 4–9 (1989)CrossRefGoogle Scholar
  9. 9.
    Mallat, S.: Multifrequency Channel Decompositions. IEEE Trans. On Acoustics, Speech and Signal Processing 37(12) (1989)Google Scholar
  10. 10.
    Vaidyanathan, P.P.: Multirate Systems and Filters Banks. Prencitce-Hall Inc., Englewood Cliffs (1993)zbMATHGoogle Scholar
  11. 11.
    Vishwanath, M.: The Recursive Pyramid Algorithm for the Discrete Wavelet Transform. IEEE Trans. On Signal Processing 42(3), 673–677 (1994)CrossRefGoogle Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2003

Authors and Affiliations

  • Guillermo Payá
    • 1
  • Marcos M. Peiró
    • 1
  • Francisco Ballester
    • 1
  • Francisco Mora
    • 1
  1. 1.Department of Electronic EngineeringUniversidad Politécnica de ValenciaSpain

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