Fully Parameterized Discrete Wavelet Packet Transform Architecture Oriented to FPGA

  • Guillermo Payá
  • Marcos M. Peiró
  • Francisco Ballester
  • Francisco Mora
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2778)


The present paper describes a fully parameterized Discrete Wavelet Packet Transform (DWPT) architecture based on a folded Distributed Arithmetic implementation, which makes possible to design any kind of wavelet bases. The proposed parameterized architecture allows different CDF wavelet coefficient with variable bit precision (data input and output size, and coefficient length). Moreover, by combining different blocks in cascade, we can expand as many complete stages (wavelet packet levels) as we require. Our architecture need only two FIR filters to calculate various wavelet stages simultaneously, and specific VIRTEX family resources (SRL16E) have been instantiated to reduce area and increase frequency operation. Finally, a DWPT implementation for CDF(9,7) wavelet coefficients is synthesized on VIRTEX-II 3000-6 FPGA for different precisions.


Discrete Wavelet Transform Wavelet Packet Wavelet Packet Transform Quadrature Mirror Filter Distribute Arithmetic 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Springer-Verlag Berlin Heidelberg 2003

Authors and Affiliations

  • Guillermo Payá
    • 1
  • Marcos M. Peiró
    • 1
  • Francisco Ballester
    • 1
  • Francisco Mora
    • 1
  1. 1.Department of Electronic EngineeringUniversidad Politécnica de ValenciaSpain

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