Improving DSP Performance with a Small Amount of Field Programmable Logic

  • John Oliver
  • Venkatesh Akella
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2778)


We show a systematic methodology to create DSP + field-programmable logic hybrid architectures by viewing it as a hardware/software codesign problem. This enables an embedded processor architect to evaluate the trade-offs in the increase in die area due to the field programmable logic and the resultant improvement in performance or code size. We demonstrate our methodology with the implementation of a Viterbi decoder. A key result of the paper is that the addition of a field-programmable data alignment unit (FPDAU) between the register-file and the computational blocks provides 15%-22% improvement in the performance of a Viterbi decoder on the state-of-the-art TigerSHARC DSP. The area overhead of the FPDAU is small relative to the DSP die size and does not require any changes to the programming model or the instruction set architecture.


State Machine Programmable Logic Register File Hardware Overhead Viterbi Decoder 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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  1. 1.
    Stitt, G., Vahid, F.: Energy Advantages of Microprocessor Platforms with On-chip Configurable Logic. IEEE Design and Test (2002)Google Scholar
  2. 2.
    Ye, Z., Moshovos, A., Hauck, S., Banerjee, P.: CHIMAERA: A High-Performance Architecture with a Tightly-Coupled Reconfigurable Functional Unit. Computer Architecture News (2000)Google Scholar
  3. 3.
    Graham, P., Nelson, B.: Reconfigurable Processors for High-Performance, Embedded Digital Signal Processing. In: Lysaght, P., Irvine, J., Hartenstein, R.W. (eds.) FPL 1999. LNCS, vol. 1673, pp. 1–10. Springer, Heidelberg (1999)CrossRefGoogle Scholar
  4. 4.
    Fisher, J., Faraboschi, P., Desoli, G.: Custom-Fit Processors: Letting Applications Define Architectures. Hewlett-Packard Laboratories Cambridge, Cambridge (1996)Google Scholar
  5. 5.
    Compton, K., Hauck, S.: Reconfigurable Computing: A Survey of Systems and Software,
  6. 6.
    Dehon, A.: The Density Advantage of Configurable Computing. IEEE Computer Magazine (2000)Google Scholar
  7. 7.
    Tessier, R., Burleson, R.: Reconfigurable Computing for Digital Signal Processing: A Survey. Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology (2001)Google Scholar
  8. 8.
    Hartenstein, R.: Reconfigurable Computing: A New Business Model – and it’s Impact on SoC Design. In: Proceedings Euromicro Symposium on Digital Systems Design, IEEE Comput. Soc., Los Alamitos (2001)Google Scholar
  9. 9.
  10. 10.
    Analog Devices: TigerSHARC DSP Hardware Specification,
  11. 11.
    Fridman, J.: Data Alignment for Sub-Word Parallelism in DSP. IEEE Signal Processing Magazine, IEEE, 27–35 (2000)Google Scholar
  12. 12.
    Texas Instruments: TMS320C6000 CPU and Instruction Set Reference Guide (2000),
  13. 13.
    Razdan, R., Smith, M.: High-Performance Microarchitectures with Hardware- Programmable Functional Units. In: Proc. 27th Annual IEEE/ACM Intl. Symp. on Microarchitecture, pp. 172–180 (November 1994)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2003

Authors and Affiliations

  • John Oliver
    • 1
  • Venkatesh Akella
    • 1
  1. 1.Department of Electrical & Computer EngineeringUniversity of CaliforniaDavisUSA

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