Advertisement

Fault Tolerance Analysis of Distributed Reconfigurable Systems Using SAT-Based Techniques

  • Rainer Feldmann
  • Christian Haubelt
  • Burkhard Monien
  • Jürgen Teich
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2778)

Abstract

The ability to migrate tasks from one reconfigurable node to another improves the fault tolerance of distributed reconfigurable systems. The degree of fault tolerance is inherent to the system and can be optimized during system design. Therefore, an efficient way of calculating the degree of fault tolerance is needed. This paper presents an approach based on satisfiability testing (SAT) which regards the question: How many resources may fail in a distributed reconfigurable system without losing any functionality? We will show by experiment that our new approach can easily be applied to systems of reasonable size as we will find in the future in the field of body area networks and ambient intelligence.

Keywords

Boolean Function Fault Tolerance Task Graph Mapping Edge Boolean Formula 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. 1.
    Dick, R., Jha, N.: CORDS: Hardware-Software Co-Synthesis of Reconfigurable Real-Time Distributed Embedded Systems. In: Proceedigns of ICCAD 1998, pp. 62–68 (1998)Google Scholar
  2. 2.
    Ouaiss, I., Govindarajan, S., Srinivasan, V., Kaul, M., Vemuri, R.: An Integrated Partitioning and Synthesis System for Dynamically Reconfigurable Multi-FPGA Architectures. In: IPPS/SPDP Workshops, pp. 31–36 (1998)Google Scholar
  3. 3.
    Walder, H., Platzner, M.: Online Scheduling for Block-partitioned Reconfigurable Devices. In: Proceedings of Design, Automation and Test in Europe (DATE 2003), pp. 290–295 (2003)Google Scholar
  4. 4.
    Rintanen, J.: Constructing Conditional Plans by a Theorem-Prover. Journal of Artificial Intelligence 10, 323–352 (1999)MathSciNetCrossRefGoogle Scholar
  5. 5.
    Egly, U., Eiter, T., Tompits, H., Woltran, S.: Solving Advanced Reasoning Tasks Using Quantified Boolean Formulas. In: Proc. of the 17th Nat. Conf. on Artificial Intelligence, pp. 417–422 (2000)Google Scholar
  6. 6.
    Scholl, C., Becker, B.: Checking Equivalence for Partial Implementations. In: Proceedings of 38th Design Automation Conference, Las Vegas, USA, pp. 238–243 (2001)Google Scholar
  7. 7.
    Kleine-Büning, H., Karpinski, M., Flögel, A.: Resolution for Quantified Boolean Formulas. Information and Computation 117, 12–18 (1995)MathSciNetCrossRefGoogle Scholar
  8. 8.
    Cadoli, M., Giovanardi, A., Schaerf, M.: An Algorithm to Evaluate Quantified Boolean Formulae. In: Proc. of the 15th Nat. Conf. on Artificial Intelligence, pp. 262–267 (1998)Google Scholar
  9. 9.
    Feldmann, R., Monien, B., Schamberger, S.: A Distributed Algorithm to Evaluate Quantified Boolean Formulas. In: Proc. of the 17th Nat. Conf. on Artificial Intelligence, pp. 285–290 (2000)Google Scholar
  10. 10.
    Giunchiglia, E., Narizzano, M., Tacchella, A.: Backjumping for Quantified Boolean Formulas. In: Proc. of the 17th Int. Joint Conf. on Artificial Intelligence, pp. 275–281 (2001)Google Scholar
  11. 11.
    Cadence: Virtual Component Co-design (VCC) (2001), http://www.cadence.com
  12. 12.
    Blickle, T., Teich, J., Thiele, L.: System-Level Synthesis Using Evolutionary Algorithms. In: Gupta, R. (ed.) Design Automation for Embedded Systems, vol. 3, pp. 23–62. Kluwer Academic Publishers, Boston (1998)Google Scholar
  13. 13.
    Baumgarte, V., May, F., Nückel, A., Vorbach, M., Weinhardt, M.: PACT XPP - A Self- Reconfigurable Data Processing Architecture. In: ERSA, Las Vegas, Nevada (2001)Google Scholar
  14. 14.
    Chameleon Systems: CS 2000 Reconfigurable Communications Processor (2000)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2003

Authors and Affiliations

  • Rainer Feldmann
    • 1
  • Christian Haubelt
    • 2
  • Burkhard Monien
    • 1
  • Jürgen Teich
    • 2
  1. 1.AG Monien, Faculty of CS, EE, and MathematicsUniversity of PaderbornGermany
  2. 2.Department of Computer Science 12, Hardware-Software-Co-DesignUniversity of Erlangen-NurembergGermany

Personalised recommendations