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Heterogeneous Logic Block Architectures for Via-Patterned Programmable Fabrics

  • Aneesh Koorapaty
  • Lawrence Pileggi
  • Herman Schmit
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2778)

Abstract

ASIC designs are becoming increasingly unaffordable due to rapidly increasing mask costs, greater manufacturing complexity, and the need for several re-spins to meet design constraints. Although FPGAs solve the NRE cost problem, they often fail to achieve the required performance and density. A Via-Patterned Gate Array (VPGA) that combines the regularity and design cost amortization benefits of FPGAs with silicon area and power consumption comparable to ASICs, was presented in [1]. The VPGA fabric consists of a regular interconnect architecture laid on top of an array of patternable logic blocks (PLBs). Customization of the logic and interconnect is done by the placement or removal of vias at a subset of the potential via locations. In this paper, we propose four heterogeneous PLBs for via-patterned fabrics and explore their performance, density and fabric utilization characteristics across several applications. Although this analysis is done in the context of the VPGA fabric, the proposed heterogeneous PLBs and the experimental methodology can be employed for any embedded programmable fabric.

Keywords

Logic Gate Primary Input Logic Element Programmable Fabric Nand Gate 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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References

  1. 1.
    Pileggi, L., Schmit, H., Shah, J.T., Tong, K.Y., Patel, C., Chandra, V.: A Via Patterned Gate Array (VPGA), Technical Report Series, Center for Silicon System Implementation, No. CSSI 02-15 (March 2002)Google Scholar
  2. 2.
    Koorapaty, A., Pileggi, L.: Modular, Fabric-specific Synthesis for Programmable Architectures. In: Glesner, M., Zipf, P., Renovell, M. (eds.) FPL 2002. LNCS, vol. 2438, p. 132. Springer, Heidelberg (2002)CrossRefGoogle Scholar
  3. 3.
    Koorapaty, A., Chandra, V., Tong, K.Y., Patel, C., Pileggi, L., Schmit, H.: Heterogeneous Programmable Logic Block Architectures. In: Proceedings of Design Automation and Test in Europe (March 2003)Google Scholar
  4. 4.
    Patel, C., Cozzie, A., Schmit, H., Pileggi, L.: An Architectural Exploration of Via Patterned Gate Arrays. In: ACM/SIGDA International Symposium on Physical Design (2003)Google Scholar
  5. 5.
    He, J., Rose, J.: Advantages of Heterogeneous Logic Block Architectures for FPGAs. In: IEEE Custom Integrated Circuits Conference, pp. 7.4.1–7.4.5 (May 1993)Google Scholar
  6. 6.
    Betz, V., Rose, J.: Cluster-Based Logic Blocks for FPGAs: Area-Efficiency vs. Input Sharing and Size. In: IEEE Custom Integrated Circuits Conference, pp. 551–554 (1997)Google Scholar
  7. 7.
    Betz, V., Rose, J., Marquardt, A.: Architecture and CAD for Deep-Submicron FPGAs. Kluwer Academic Publishers, Dordrecht (1999)CrossRefGoogle Scholar
  8. 8.
    Kaviani, A., Brown, S.: The hybrid field-programmable architecture. IEEE Design & Test of Computers 16(2), 74–83 (1999)CrossRefGoogle Scholar
  9. 9.
    Koorapaty, A.: Modular, Fabric-specific Synthesis and Novel Logic Block Architectures for Regular Fabrics, Ph.D. Thesis, Center for Silicon System Implementation, Carnegie Mellon University (2003)Google Scholar
  10. 10.
    Pileggi, L., Schmit, H., Strojwas, A.J., Gopalakrishnan, P., Kheterpal, V., Koorapaty, A., Patel, C., Rovner, V., Tong, K.Y.: Exploring Regular Fabrics to Optimize the Performance-Cost Tradeoff. In: Proceedings of Design Automation Conference (June 2003)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2003

Authors and Affiliations

  • Aneesh Koorapaty
    • 1
  • Lawrence Pileggi
    • 1
  • Herman Schmit
    • 1
  1. 1.Carnegie Mellon UniversityPittsburghUSA

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