Symbol Timing Synchronization in FPGA-Based Software Radios: Application to DVB-S

  • Francisco Cardells-Tormo
  • Javier Valls-Coquillat
  • Vicenc Almenar-Terre
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2778)


The design of all-digital symbol timing synchronizers for FPGAs is a complex task. There are several architectures available for VLSI wireless transceivers but porting them to a software defined radio (SDR) platform is not straightforward. In this paper we report a receiver architecture prepared to support demanding protocols such as satellite digital video broadcast (DVB-S). In addition, we report hardware implementation and area utilization estimation. Finally we present implementation results of a DVB-S digital receiver on a Virtex-II Pro FPGA.


Symbol Rate Symbol Timing Digital Video Broadcasting Fractional Delay Symbol Detector 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Springer-Verlag Berlin Heidelberg 2003

Authors and Affiliations

  • Francisco Cardells-Tormo
    • 1
  • Javier Valls-Coquillat
    • 2
  • Vicenc Almenar-Terre
    • 3
  1. 1.Inkjet Commercial Division (ICD) R&D LabHewlett-PackardSant Cugat del Valles, BarcelonaSpain
  2. 2.Department of Electronic EngineeringPolytechnic University of Valencia (UPV)ValenciaSpain
  3. 3.Department of TelecommunicationsPolytechnic University of Valencia (UPV)ValenciaSpain

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