Software Decelerators

  • Eric Keller
  • Gordon Brebner
  • Phil James-Roxby
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2778)


This paper introduces the notion of a software decelerator, to be used in logic-centric system architectures. Functions are offloaded from logic to a processor, accepting a speed penalty in order to derive overall system benefits in terms of improved resource use (e.g. reduced area or lower power consumption) and/or a more efficient design process. The background rationale for such a strategy is the increasing availability of embedded processors ’for free’ in Platform FPGAs. A detailed case study of the concept is presented, involving the provision of a high-level technology-independent design methodology based upon a finite state machine model. This illustrates easier design and saving of logic resource, with timing performance still meeting necessary requirements.


State Machine Programmable Logic Field Programmable Gate Array Logic Resource Embed Processor 
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Copyright information

© Springer-Verlag Berlin Heidelberg 2003

Authors and Affiliations

  • Eric Keller
    • 1
  • Gordon Brebner
    • 1
  • Phil James-Roxby
    • 1
  1. 1.Xilinx Research LabsXilinx Inc.USA

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