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Software Decelerators

  • Eric Keller
  • Gordon Brebner
  • Phil James-Roxby
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2778)

Abstract

This paper introduces the notion of a software decelerator, to be used in logic-centric system architectures. Functions are offloaded from logic to a processor, accepting a speed penalty in order to derive overall system benefits in terms of improved resource use (e.g. reduced area or lower power consumption) and/or a more efficient design process. The background rationale for such a strategy is the increasing availability of embedded processors ’for free’ in Platform FPGAs. A detailed case study of the concept is presented, involving the provision of a high-level technology-independent design methodology based upon a finite state machine model. This illustrates easier design and saving of logic resource, with timing performance still meeting necessary requirements.

Keywords

State Machine Programmable Logic Field Programmable Gate Array Logic Resource Embed Processor 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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References

  1. 1.
    Baloron, F., Giusto, P., Jurecska, A., Passerone, C., Sentovich, E., Chiodo, M., Hsieh, H., Lavagno, L., Sangiovanni-Vincentelli, A.L., Suzuki, K.: Hardware-Software codesign of embedded systems: the POLIS approach. Kluwer, Dordrecht (1997)Google Scholar
  2. 2.
    Brebner, G.: Single-chip Gigabit mixed-version IP router on Virtex-II Pro. In: IEEE Symposium on FPGAs for Custom Computing Machines (FCCM 2002), April 2002, pp. 35–44 (2002)Google Scholar
  3. 3.
    Dales, M.: The Proteus processor - a conventional CPU with reconfigurable functionality. In: Lysaght, P., Irvine, J., Hartenstein, R.W. (eds.) FPL 1999. LNCS, vol. 1673, pp. 431–437. Springer, Heidelberg (1999)CrossRefGoogle Scholar
  4. 4.
    Li, Y.S., Malik, S.: Performance analysis of embedded software using implicit path enumeration. In: ACM/IEEE Design Automation Conference (DAC 1995), June 1995, pp. 456–461 (1995)Google Scholar
  5. 5.
    Sgroi, M., Sheets, M., Mihal, A., Keutzer, K., Malik, S., Rabaey, J., Sangiovanni-Vincentelli, A.: Addressing the system-on-a-chip interconnect woes through communication-based design. In: ACM/IEEE Design Automation Conference (DAC 2001), pp.667–672 (June 2001)Google Scholar
  6. 6.
    Singh, S., Slous, R.: Accelerating Adobe Photoshop with reconfigurable logic. In: IEEE Symposium on FPGAs for Custom Computing Machines (FCCM 1998), April 1998, pp. 15–17 (1998)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2003

Authors and Affiliations

  • Eric Keller
    • 1
  • Gordon Brebner
    • 1
  • Phil James-Roxby
    • 1
  1. 1.Xilinx Research LabsXilinx Inc.USA

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