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Globally Asynchronous Locally Synchronous FPGA Architectures

  • Andrew Royal
  • Peter Y. K. Cheung
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2778)

Abstract

Globally Asynchronous Locally Synchronous (GALS) Systems have provoked renewed interest over recent years as they have the potential to combine the benefits of asynchronous and synchronous design paradigms. It has been applied to ASICs, but not yet applied to FPGAs. In this paper we propose applying GALS techniques to FPGAs in order to overcome the limitation on timing imposed by slow routing.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2003

Authors and Affiliations

  • Andrew Royal
    • 1
  • Peter Y. K. Cheung
    • 1
  1. 1.Department of Electrical & Electronic EngineeringImperial CollegeLondonUK

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