Programmable Asynchronous Pipeline Arrays

  • John Teife
  • Rajit Manohar
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2778)


We discuss high-performance programmable asynchronous pipeline arrays (PAPAs). These pipeline arrays are coarse-grain field programmable gate arrays (FPGAs) that realize high data throughput with fine-grain pipelined asynchronous circuits. We show how the PAPA architecture maintains most of the speed and energy benefits of a custom asynchronous design, while also providing post-fabrication logic reconfigurability. We report results for a prototype PAPA design in a 0.25μm CMOS process that has a peak pipeline throughput of 395MHz for asynchronous logic.


Pipeline Stage Logic Cell Asynchronous System Asynchronous Circuit FPGA Architecture 
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Copyright information

© Springer-Verlag Berlin Heidelberg 2003

Authors and Affiliations

  • John Teife
    • 1
  • Rajit Manohar
    • 1
  1. 1.Computer Systems Laboratory, Electrical and Computer EngineeringCornell UniversityIthacaUSA

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