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Performance and Area Modeling of Complete FPGA Designs in the Presence of Loop Transformations

  • K. R. Shesha Shayee
  • Joonseok Park
  • Pedro C. Diniz
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2778)

Abstract

Selecting which program transformations to apply when mapping computations to FPGA-based architectures leads to prohibitively long design exploration cycles. An alternative is to develop fast, yet accurate, performance and area models to understand the impact and interaction of the transformations. In this paper we present a combined analytical performance and area modeling for complete FPGA designs in the presence of loop transformations. Our approach takes into account the impact of input/output memory bandwidth and memory interface resources, often the limiting factor in the effective implementation of these computations. Our preliminary results reveal that our modeling is very accurate allowing a compiler tool to quickly explore a very large design space resulting in the selection of a feasible high-performance design.

Keywords

Memory Access Area Modeling Loop Nest Synthesis Tool FPGA Device 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2003

Authors and Affiliations

  • K. R. Shesha Shayee
    • 1
  • Joonseok Park
    • 1
  • Pedro C. Diniz
    • 1
  1. 1.Information Sciences InstituteUniversity of Southern CaliforniaMarina del ReyUSA

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