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An FPGA-Based Performance Analysis of the Unrolling, Tiling, and Pipelining of the AES Algorithm

  • G. P. Saggese
  • A. Mazzeo
  • N. Mazzocca
  • A. G. M. Strollo
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2778)

Abstract

In October 2000 the National Institute of Standards and Technology chose Rijndael algorithm as the new Advanced Encryption Standard (AES). AES finds wide deployment in a huge variety of products making efficient implementations a significant priority. In this paper we address the design and the FPGA implementation of a fully key agile AES encryption core with 128-bit keys. We discuss the effectiveness of several design techniques, such as accurate floorplanning, the unrolling, tiling and pipelining transformations (also in the case of feedback modes of operation) to explore the design space. Using these techniques, four architectures with different level of parallelism, trading off area for performance, are described and their implementations on a Virtex-E FPGA part are presented. The proposed implementations of AES achieve better performance as compared to other blocks in the literature and commercial IP core on the same device.

Keywords

Block Cipher Advance Encryption Standard Advance Encryption Standard Algorithm Cipher Block Chain Cipher Algorithm 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2003

Authors and Affiliations

  • G. P. Saggese
    • 1
  • A. Mazzeo
    • 1
  • N. Mazzocca
    • 2
  • A. G. M. Strollo
    • 1
  1. 1.University of Naples Federico IINapoliItaly
  2. 2.Second University of NaplesAversaItaly

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