Efficient Modular-Pipelined AES Implementation in Counter Mode on ALTERA FPGA

  • François Charot
  • Eslam Yahya
  • Charles Wagner
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2778)


This paper describes a high performance single-chip FPGA implementation of the new Advanced Encryption Standard (AES) algorithm dealing with 128-bit data/key blocks and operating in Counter (CTR) mode. Counter mode has a proven-tight security and it enables the simultaneous processing of multiple blocks without losing the feedback mode advantages. It also gives the advantage of allowing the use of similar hardware for both encryption and decryption parts. The proposed architecture is modular. The architecture basic module implements a single round of the algorithm with the required expansion hardware and control signals. It gives very high flexibility in choosing the degree of pipelining according to the throughput requirements and hardware limitations and this gives the ability to achieve the best compromised design due to these aspects. The FPGA implementation presented is that of a pipelined single chip Rijndael design which runs at a rate of 10.8 Gbits/sec for full pipelining on an ALTERA APEX-EP20KE platform.


Block Cipher Advance Encryption Standard FPGA Implementation Input Block Decryption Part 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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  1. 1.
    Altera APEX20K, APEX 20K Devices: System-on-a-Programmable-Chip Solutions,
  2. 2.
    Daemen, J., Rijmen, V.: The Rijndael Block Cipher: AES Proposal. In: First AES Candidate Conference (AES1) (Augusts 1998)Google Scholar
  3. 3.
    Dworkin, M.: Recommendation for Block Cipher Modes of Operation. NIST special Publication 800-38A (December 2001)Google Scholar
  4. 4.
    Elbirt, A.J., Yip, W., Chetwynd, B., Paar, C.: An FPGA Implementation and Performance Evaluation of the AES Block Cipher Candidate Algorithm Finalists. In: The Third AES Candidate Conference (AES3) (April 2000)Google Scholar
  5. 5.
    FIPS Publication 197, Specification for the Advanced Encryption Standard (AES), Federal Information Processing Standards Publication 197, U.S. DoC/NIST (November 2001)Google Scholar
  6. 6.
    Kuo, H., Verbauwhe, I.: Architectural Optimisation for a 1.82Gbits/sec VLSI Implementation of the AES Rijndael Algorithm. In: Koç, Ç.K., Naccache, D., Paar, C. (eds.) CHES 2001. LNCS, vol. 2162, p. 51. Springer, Heidelberg (2001)CrossRefGoogle Scholar
  7. 7.
    Lipmaa, H., Rogaway, P., Wagner, D.: Comments to NIST concerning AES Modes of Operations CTR-Mode Encryption. In: Symmetric Key Block Cipher Modes of Operation Workshop (October 2000)Google Scholar
  8. 8.
    McLoone, M., McCanny, J.V.: High Performance Single-Chip FPGA Rijndael Algorithm Implementations. In: Koç, Ç.K., Naccache, D., Paar, C. (eds.) CHES 2001. LNCS, vol. 2162, p. 65. Springer, Heidelberg (2001)CrossRefGoogle Scholar
  9. 9.
    Alam, M., Badawy, W., Jullien, G.: A Novel Pipelined Threads Architecture for AES Encryption Algorithm. In: ASAP 2002 (July 2002)Google Scholar
  10. 10.
    Report on the Symmetric Key Block Cipher Modes of Operations Workshop (NIST) (October 2000)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2003

Authors and Affiliations

  • François Charot
    • 1
  • Eslam Yahya
    • 2
  • Charles Wagner
    • 1
  1. 1.IRISA/INRIA Campus de BeaulieuRennes CedexFrance
  2. 2.Information Technology Institute-ITIBenha High Institute of Technology-BHITBenhaEgypt

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