Encoded-Low Swing Technique for Ultra Low Power Interconnect
We present a novel encoded-low swing technique for ultra low power interconnect. Using this technique and an efficient circuit implementation, we achieve an average of 45.7% improvement in the power-delay product over the schemes utilizing low swing techniques alone, for random bit streams. Also, we obtain an average of 75.8% improvement over the schemes using low power bus encoding alone. We present extensive simulation results, including the driver and receiver circuitry, over a range of capacitive loads, for a general test interconnect circuit and also for a FPGA test interconnect circuit. Analysis of the results prove that as the capacitive load over the interconnect increases, the power-delay product for the proposed technique outperforms the techniques based on either low swing or bus encoding. We also present the signal to noise ratio (SNR) analysis using this technique for a CMOS 0.13μm process and prove that there is a 8.8% improvement in the worst case SNR compared to low swing techniques. This is a consequence of the reduction in the signal switching over the interconnect which leads to lower power supply noise.
KeywordsCapacitive Load Delay Product Test Architecture Power Supply Noise Crosstalk Noise
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