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Encoded-Low Swing Technique for Ultra Low Power Interconnect

  • Rohini Krishnan
  • Jose Pineda de Gyvez
  • Harry J. M. Veendrick
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2778)

Abstract

We present a novel encoded-low swing technique for ultra low power interconnect. Using this technique and an efficient circuit implementation, we achieve an average of 45.7% improvement in the power-delay product over the schemes utilizing low swing techniques alone, for random bit streams. Also, we obtain an average of 75.8% improvement over the schemes using low power bus encoding alone. We present extensive simulation results, including the driver and receiver circuitry, over a range of capacitive loads, for a general test interconnect circuit and also for a FPGA test interconnect circuit. Analysis of the results prove that as the capacitive load over the interconnect increases, the power-delay product for the proposed technique outperforms the techniques based on either low swing or bus encoding. We also present the signal to noise ratio (SNR) analysis using this technique for a CMOS 0.13μm process and prove that there is a 8.8% improvement in the worst case SNR compared to low swing techniques. This is a consequence of the reduction in the signal switching over the interconnect which leads to lower power supply noise.

Keywords

Capacitive Load Delay Product Test Architecture Power Supply Noise Crosstalk Noise 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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References

  1. 1.
    Zhang, H., et al.: Low-Swing On-Chip Signaling Techniques: Effectiveness and Robustness. IEEE Transactions on VLSI systems 8(3), 264–272 (2000)CrossRefGoogle Scholar
  2. 2.
    Nakamura, K., et al.: A 50% Noise Reduction Interface Using Low-Weight Coding. In: 1996 Symposium on VLSI Circuits Digest of Technical Papers, pp. 144–145 (1996)Google Scholar
  3. 3.
    Stan, M.R.: Bus-Invert Coding for Low-Power I/O. IEEE Transactions on VLSI systems 3(1), 49–58 (1995)CrossRefGoogle Scholar
  4. 4.
    Dally, W., Poulton, J.: Digital Systems Engineering. Cambridge Univ. Press, Cambridge (1998)CrossRefGoogle Scholar
  5. 5.
    Rose, J.: Vaughn Betz Architecture and CAD for deep-submicron FPGAs,Google Scholar
  6. 6.
    George, V., et al.: Design of a low energy FPGA. In: International Symposium On Low Power Electronics and Design, pp.188-193 (1999)Google Scholar
  7. 7.
    Liu, D., et al.: Power consumption estimation in CMOS VLSI chips. IEEE Journal Solid-State Circuits 29, 663–670 (1994)CrossRefGoogle Scholar
  8. 8.
    Kusse, E.: Analysis and circuit design for low power programmable logic modules., M.S. thesis, Univ. Calif., Berkeley (1997)Google Scholar
  9. 9.
    Musoll, E., et al.: Working-zone encoding for reducing the energy in microprocessor address buses. IEEE Transactions on VLSI Systems 6(4), 568–572 (1998)CrossRefGoogle Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2003

Authors and Affiliations

  • Rohini Krishnan
    • 1
  • Jose Pineda de Gyvez
    • 1
  • Harry J. M. Veendrick
    • 1
  1. 1.Philips Research LaboratoriesEindhovenThe Netherlands

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