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Data Processing System with Self-reconfigurable Architecture, for Low Cost, Low Power Applications

  • Michael G. Lorenz
  • Luis Mengibar
  • Luis Entrena
  • Raul Sánchez-Reillo
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2778)

Abstract

In this paper, a low cost self-reconfigurable data processing system with a USB interface is presented. A single FPGA performs all processing and controls the multiple configurations without any additional elements, such as microprocessor, host computer or additional FPGAs. This architecture allows high performances at very low power consumption. In addition, a hierarchical reconfiguration system is used to support a large number of different processing tasks without the penalty in power consumption of a big local configuration memory. Due to its simplicity and low power, this data processing system is specially suitable for portable applications.

Keywords

Power Dissipation Host Computer Very Large Scale Integration Data Memory Data Processing System 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2003

Authors and Affiliations

  • Michael G. Lorenz
    • 1
  • Luis Mengibar
    • 1
  • Luis Entrena
    • 1
  • Raul Sánchez-Reillo
    • 1
  1. 1.Electronic Technology DepartmentUniversidad Carlos III de MadridSpain

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