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Design Strategies and Modified Descriptions to Optimize Cipher FPGA Implementations: Fast and Compact Results for DES and Triple-DES

  • Gaël Rouvroy
  • François-Xavier Standaert
  • Jean-Jacques Quisquater
  • Jean-Didier Legat
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2778)

Abstract

In this paper, we propose a new mathematical DES description that allows us to achieve optimized implementations in term of ratio Throughput/Area. First, we get an unrolled DES implementation that works at data rates of 21.3 Gbps (333 MHz), using Virtex-II technology. In this design, the plaintext, the key and the mode (encryption/decrytion) can be changed on a cycle-by-cycle basis with no dead cycles. In addition, we also propose sequential DES and triple-DES designs that are currently the most efficient ones in term of resources used as well as in term of throughput. Based on our DES and triple-DES results, we also set up conclusions for optimized FPGA design choices and possible improvement of cipher implementations with a modified structure description.

Keywords

cryptography DES FPGA efficient implementations design methodology 

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References

  1. 1.
    Rabaey, J.M.: Digital Integrated Circuits. Prentice Hall, Englewood Cliffs (1996)Google Scholar
  2. 2.
    Xilinx: Virtex 2.5V field programmable gate arrays data sheet, available from http://www.xilinx.com
  3. 3.
    Xilinx, Pasham, V., Trimberger, S.: High-Speed DES and Triple DES Encryptor/ Decryptor (August 2001), available from http://www.xilinx.com/xapp/xapp270.pdf
  4. 4.
    Schneier, B.: Applied Cryptography, 2nd edn. John Wiley & Sons, Inc., Chichester (1996)Google Scholar
  5. 5.
    National Bureau of Standards. FIPS PUB 46, The Data Encryption Standard. U.S. Departement of Commerce (January 1977)Google Scholar
  6. 6.
  7. 7.
    Patterson, C.: High performance DES encryption in Virtex FPGAs using Jbits. In: Proc. of FCCM 2001, IEEE Computer Society, Los Alamitos (2000)Google Scholar
  8. 8.
    Trimberger, S., Pang, R., Singh, A.: A 12 Gbps DES encryptor/decryptor core in an FPGA. In: Paar, C., Koç, Ç.K. (eds.) CHES 2000. LNCS, vol. 1965, pp. 156–163. Springer, Heidelberg (2000)CrossRefGoogle Scholar
  9. 9.
    Davio, M., Desmedt, Y., Fosséprez, M., Govaerts, R., Hulsbosch, J., Neutjens, P., Piret, P., Quisquater, J.J., Vandewalle, J., Wouters, P.: Analytical Characteristics of the DES. In: Chaum, D. (ed.) Advances in Cryptology - Crypto 1983, Berlin, pp. 171–202. Springer, Heidelberg (1983)Google Scholar
  10. 10.
    Helion Technology. High Performance DES and Triple-DES Core for XILINX FPGA, available from http://www.heliontech.com
  11. 11.
    CAST, Inc. Triple DES Encryption Core, available from http://www.cast-inc.com
  12. 12.
    CAST, Inc. DES Encryption Core, available from http://www.cast-inc.com
  13. 13.
    inSilicon. X–3 DES Triple DES Cryptoprocessor, available from http://www.insilicon.com
  14. 14.
    inSilicon. X DES Cryptoprocessor, available from http://www.insilicon.com
  15. 15.
    Chodowiec, P., Gaj, K., Bellows, P., Schott, B.: Experimental Testing of the Gigabit IPSec-Compliant Implementations of RIJNDAEL and Triple DES Using SLAAC-1V FPGA Accelerator Board. In: Davida, G.I., Frankel, Y. (eds.) ISC 2001. LNCS, vol. 2200, pp. 220–234. Springer, Heidelberg (2001)CrossRefGoogle Scholar
  16. 16.
    Kaps, J.P., Paar, C.: Fast DES Implementations for FPGAs and Its Application to a Universal Key-Search Machine. In: Tavares, S., Meijer, H. (eds.) SAC 1998. LNCS, vol. 1556, pp. 234–247. Springer, Heidelberg (1999)CrossRefGoogle Scholar
  17. 17.
    Rouvroy, G., Standaert, F., Quisquater, J., Legat, J.: Efficient Uses of FPGA’s for Implementations of DES and its Experimental Linear Cryptanalysis. Accepted for publication on April 2003 in IEEE Transactions on Computers, Special CHES Edition (2003)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2003

Authors and Affiliations

  • Gaël Rouvroy
    • 1
  • François-Xavier Standaert
    • 1
  • Jean-Jacques Quisquater
    • 1
  • Jean-Didier Legat
    • 1
  1. 1.UCL Crypto Group, Laboratoire de MicroélectroniqueUniversité catholique de LouvainLouvain-La-NeuveBelgium

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