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Reducing the Configuration Loading Time of a Coarse Grain Multicontext Reconfigurable Device

  • Toshiro Kitaoka
  • Hideharu Amano
  • Kenichiro Anjo
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2778)

Abstract

High speed and low cost configuration loading methods for a coarse grain multicontext reconfigurable device DRP(Dynamically Reconfigurable Processor) are proposed and implemented. In these methods, the configuration data is compressed on the host computer before loading, and decoded at the time of loading by circuits implemented on a part of logics. Unlike conventional reconfigurable device, the logic for decoder circuits is switched with application circuits immediately after loading in multicontext reconfigurable devices. Thus, the circuit does not use a real estate of the chip during the execution. Two compression methods LZSS-ARC and Selective coding are implemented and evaluated. LZSS-ARC achieves better compression ratio, while Selective coding can work at the same frequency of the data loading.

Keywords

Clock Cycle Compression Technique Compression Method Context Switching Loading Time 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2003

Authors and Affiliations

  • Toshiro Kitaoka
    • 1
  • Hideharu Amano
    • 1
  • Kenichiro Anjo
    • 2
  1. 1.Dept. of ICSKeio UniversityJapan
  2. 2.NEC ElectronicsJapan

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