A Dynamically Adaptive Switching Fabric on a Multicontext Reconfigurable Device

  • Hideharu Amano
  • Akiya Jouraku
  • Kenichiro Anjo
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2778)


A framework of dynamically adaptive hardware mechanism on multicontext reconfigurable devices is proposed, and as an example, an adaptive switching fabric is implemented on NEC’s novel reconfigurable device DRP(Dynamically Reconfigurable Processor).

In this switch, contexts for the full crossbar and alternative hardware modules, which provide larger bandwidth but can treat only a limited pattern of packet inputs, are prepared. Using the quick context switching functionality, a context for the full crossbar is switched by alternative contexts according to the packet inputs pattern. Furthermore, if the traffic includes a lot of packets for specific destinations, a set of contexts frequently used in the traffic is gathered inside the chip like a working set stored in a cache.

4 x 4 mesh network connected with the proposed adaptive switches is simulated, and it appears that the latency between nodes is improved three times when the traffic between neighboring four nodes is dominant.


Input Port Context Switching Instruction Pointer Switching Fabric Hardware Module 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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  1. 1.
    Motomura, M.: A Dynamically Reconfigurable Processor Architecture. Microprocessor Forum (October 2002)Google Scholar
  2. 2.
    Master, P.: The Age of Adaptive Computing Is Here. In: Proc. of FCCM, pp.1–3 (2002)Google Scholar
  3. 3.
    Smit, G.J.M., Havinga, P.J.M., Smit, L.T., Heysters, P.M.: Dynamic Reconfiguration in Mobile Systems. In: Glesner, M., Zipf, P., Renovell, M. (eds.) FPL 2002. LNCS, vol. 2438, pp. 162–170. Springer, Heidelberg (2002)CrossRefGoogle Scholar
  4. 4.
    Horta, E.L., Lockwood, J.W., Partour, D.: Dynamic Hardware Plugins in an FPGA with Partial Run-time Reconfiguration. In: Proc. of DAC 2002 (June 2002)Google Scholar
  5. 5.
    Ling, X.-P., Amano, H.: WASMII: A Data Driven Computer on a Virtual Hardware. In: Proc. FCCM, pp. 33–42 (1993)Google Scholar
  6. 6.
    Trimberger, S., Carberry, D., Johnson, A., Wong, J.: A Time-Multiplexed FPGA. In: Proc. FCCM pp.22-28 (1997)Google Scholar
  7. 7.
    Kaneko, N., Amano, H.: A General Hardware Design Model for Multicontext FPGAs. In: Glesner, M., Zipf, P., Renovell, M. (eds.) FPL 2002. LNCS, vol. 2438, pp. 1037–1047. Springer, Heidelberg (2002)CrossRefGoogle Scholar
  8. 8.
    Nishimura, S., et al.: High-speed network switch RHiNET-2/SW and its implementation with optical interconnections. Hot Interconnects 8, 31–38 (2000)Google Scholar
  9. 9.
    Brebner, G.: The Swappable Logic Unit: a Paradigm for Virtual Hardware. In: Proc. of FCCM, pp.82–91 (1997)Google Scholar
  10. 10.
    Li, Z., Compton, K., Hauck, S.: Configuration Caching Management Techniques for Reconfigurable Computing. In: Proc. of FCCM, pp.22–36 (2000)Google Scholar
  11. 11.
    Higuchi, T., Kajihara, N.: Evolvable hardware chips for industrial applications. Commun. ACM 42(3), 60–66 (1999)CrossRefGoogle Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2003

Authors and Affiliations

  • Hideharu Amano
    • 1
  • Akiya Jouraku
    • 1
  • Kenichiro Anjo
    • 2
  1. 1.Dept. of ICSKeio UniversityJapan
  2. 2.NEC ElectronicsJapan

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