Virtualizing Hardware with Multi-context Reconfigurable Arrays

  • Rolf Enzler
  • Christian Plessl
  • Marco Platzner
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2778)


In contrast to processors, current reconfigurable devices totally lack programming models that would allow for device independent compilation and forward compatibility. The key to overcome this limitations is hardware virtualization. In this paper, we resort to a macro-pipelined execution model to achieve hardware virtualization for data streaming applications. As a hardware implementation we present a hybrid multi-context architecture that attaches a coarse-grained reconfigurable array to a host CPU. A co-simulation framework enables cycle-accurate simulation of the complete architecture. As a case study we map an FIR filter to our virtualized hardware model and evaluate different designs. We discuss the impact of the number of contexts and the feature of context state on the speedup and the CPU load.


Data Block Context Switch Logical Context Arithmetic Logic Unit Hardware Virtualization 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Springer-Verlag Berlin Heidelberg 2003

Authors and Affiliations

  • Rolf Enzler
    • 1
  • Christian Plessl
    • 1
  • Marco Platzner
    • 1
  1. 1.Swiss Federal Institute of Technology (ETH)ZurichSwitzerland

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