Advertisement

Global Routing for Lookup-Table Based FPGAs Using Genetic Algorithms

  • Jorge Barreiros
  • Ernesto Costa
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2778)

Abstract

In this paper we present experiments concerning the feasibility of using genetic algorithms to efficiently build the global routing in lookup-table based FPGAs. The algorithm is divided in two steps: first, a set of viable routing alternatives is pre-computed for each net, and then the genetic algorithm selects the best routing for each one of the nets that offers the best overall global routing. Our results are comparable to other available global routers, so we conclude that genetic algorithms can be used to build competitive global routing tools.

Keywords

Genetic Algorithm Field Programmable Gate Array Design Automation Decomposition Tree Technology Mapping 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. 1.
    Lemieux, G., Brown, S., Vranesic, D.: On two-step routing for FPGAs. In: International Symposium on Physical Design (Abril 1997)Google Scholar
  2. 2.
    Goldber, D.: Genetic Algorithms in Search, optimization and machine learning. Addison Wesley, Reading (1989)Google Scholar
  3. 3.
    Mitchel, M.: An introduction to Genetic Algorithms. MIT Press, Cambridge (1996)Google Scholar
  4. 4.
    Alexander, M., Robins, G.: New performance-driven FPGA routing algorithms. In: Design Automation Conference (June 1995)Google Scholar
  5. 5.
    Brown, G., Rose, Z., Vranesic, G.: A detailed router for Field-Programmable gate arrays. IEEE Transactions on Computer-Aided Design 11(5) (May 1992)Google Scholar
  6. 6.
    Palczewski, M.: Plane parallel A* maze router and it’s application to FPGA’s. In: Proceedings of the Design Automation Conference (1992)Google Scholar
  7. 7.
    Alexander, M., Robins, G.: New performance-driven FPGA routing algorithms. In: Design Automation Conference (June 1995)Google Scholar
  8. 8.
    Alexander, M., Cohoon, J., Ganley, J., Robins, G.: Performance-oriented placement and routing for Field-Programmable gate arrays. In: European Design Automation Conference (September 1995)Google Scholar
  9. 9.
    Alexander, M., Robins, G.: New performance-driven FPGA routing algorithms. IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems 15(12) (December 1996)Google Scholar
  10. 10.
    Betz, V., Rose, J.: Directional bias and Non-uniformity in FPGA global routing architectures. In: IEEE/ACM International Conference on Computer Aided Design (1996)Google Scholar
  11. 11.
    Rose, J.: LocusRoute: A parallel global router for standard cells. In: Proceedings of the Design Automation Conference (1988)Google Scholar
  12. 12.
    Lemieux, G., Brown, S.: A detailed routing algorithm for allocating wire segments in field-programmable gate arrays. In: Proceedings of the ACM Physical Design Workshop (1993)Google Scholar
  13. 13.
    Lee, Y., Wu, A.: A performance and routability driven router for FPGAs considering path delays. IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems 16(2) (February 1997)Google Scholar
  14. 14.
    Cong, J., Wu, C.: Optimal FPGA mapping and retiming with efficient initial state computation. In: Proceedings of the 35th Design Automation Conference (1998)Google Scholar
  15. 15.
    Chang, S.-C., Marek-Sadowska, M., Hwang, T.: Technology mapping for TLU FPGA’s based on decomposition of binary decision diagrams. IEEE Transactions on computer aided design of integrated circuits and systems 15(10) (1996)Google Scholar
  16. 16.
    Chen, C.-S., Tsay, Y.-W., Hwang, T., Wu, A., Lin, Y.-L.: Combining technology mapping and placement for delay-minimization in FPGA designs. IEEE, Los AlamitosGoogle Scholar
  17. 17.
    Mazumder, P., Rudnik, E.: Genetic Algorithms for VLSI design, layout & test automation. Prentice Hall, Englewood Cliffs (1999): ISBN 0-13-011566-5Google Scholar
  18. 18.
    Dijkstra, E.W.: A note on two problems in connection with graphs. Numerische Mathematik 1 (1959)Google Scholar
  19. 19.
    CAD Benchmarking Laboratory, North Carolina State University, LGSynth93 suite, http://www.cbl.ncsu.edu/www/

Copyright information

© Springer-Verlag Berlin Heidelberg 2003

Authors and Affiliations

  • Jorge Barreiros
    • 1
    • 1
  • Ernesto Costa
    • 2
  1. 1.Departamento de Engenharia Informática e SistemasInstituto Superior de Engenharia de CoimbraPortugal
  2. 2.Centro de Informática e Sistemas da, Universidade de CoimbraPortugal

Personalised recommendations