Designing, Scheduling, and Allocating Flexible Arithmetic Components

  • Vinu Vijay Kumar
  • John Lach
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2778)


This paper introduces new scheduling and allocation algorithms for designing with hybrid arithmetic component libraries composed of both operation-specific components and flexible components capable of executing multiple operations. The flexible components are implemented primarily in fixedlogic with only small amounts of application-specific reconfigurability, which provides the flexibility needed without the negative area and performance penalties commonly associated with general-purpose reconfigurable arrays. Results obtained with hybrid library scheduling and allocation on a variety of digital signal processing (DSP) filters reveal that significant area savings are achieved.


Digital Signal Processing Allocation Algorithm List Schedule Data Flow Graph Area Saving 
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  1. 1.
    Chiricescu, S., et al.: Morphable multipliers. In: Glesner, M., Zipf, P., Renovell, M. (eds.) FPL 2002. LNCS, vol. 2438, pp. 647–656. Springer, Heidelberg (2002)CrossRefGoogle Scholar
  2. 2.
    Savoj, H., et al.: Boolean Matching in Logic Synthesis. In: Proceedings of the European Design Automation Conference, 168–174 (1992)Google Scholar
  3. 3.
    Paulin, P.G., Knight, J.P.: Force-Directed Scheduling for the Behavioral Synthesis of ASIC’s. IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems 8(6), 661–679 (1989)CrossRefGoogle Scholar
  4. 4.
    Verhaegh, W.F.J., et al.: Improved Force-Directed Scheduling in High-Throughput Digital Signal Processing. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 14(8), 945–960 (1995)CrossRefGoogle Scholar
  5. 5.
    Haralick, R.M., Shapiro, L.G.: Computer and Vision. Addison-Wesley, Reading (1992)Google Scholar
  6. 6.
    Högstedt, K., Orailoglu, A.: Integrating Binding Constraints in the Synthesis of Area-Efficient Self-Recovering Microarchitectures. In: Proceedings of the International Conference on Computer Design, 331–334 (1994)Google Scholar
  7. 7.
    Karri, R., Orailoglu, A.: High-Level Synthesis of Fault-Secure Microarchitectures. In: Proceedings of the Design Automation Conference, 429–433 (1993)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2003

Authors and Affiliations

  • Vinu Vijay Kumar
    • 1
  • John Lach
    • 1
  1. 1.Department of Electrical and Computer EngineeringUniversity of VirginiaCharlottesvilleUSA

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