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APPLES: A Full Gate-Timing FPGA-Based Hardware Simulator

  • Damian Dalton
  • Vivian Bessler
  • Jeffery Griffiths
  • Andrew McCarthy
  • Abhay Vadher
  • Rory O’Kane
  • Rob Quigley
  • Declan O’Connor
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2778)

Abstract

Verification of large VLSI digital circuits is primarily accomplished through simulation. In general, there is a trade-off between speed of processing and accuracy. Software simulation tools can be very accurate but are very slow compared to logic accelerators and emulation systems. These latter systems, many FPGA based, while two to three orders of magnitude faster than software, deliver inferior timing analysis, in the latter case and cycle-based simulation it is merely equivalent to functional simulation. APPLES (Associative Parallel Processor for Logic Event-driven Simulation) is the first Full Gate-timing Logic Hardware Simulator, implemented in Xilinx Virtex-II technology. APPLES is a true simulator, delivering timing analysis with the accuracy of a software simulator, but has the distinction that processing is executed entirely in hardware devoid of any machine code. This has the potential to permit APPLES to be one to two orders of magnitude faster than equivalent software systems.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2003

Authors and Affiliations

  • Damian Dalton
    • 1
  • Vivian Bessler
    • 1
  • Jeffery Griffiths
    • 1
  • Andrew McCarthy
    • 1
  • Abhay Vadher
    • 1
  • Rory O’Kane
    • 1
  • Rob Quigley
    • 1
  • Declan O’Connor
    • 1
  1. 1.Neosera Systems LtdDublin 4Ireland

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