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Custom Tag Computation Circuit for a 10Gbps SCFQ Scheduler

  • Brendan McAllister
  • Sakir Sezer
  • Ciaran Toal
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2778)

Abstract

This paper details the architecture and implementation of a tag computation circuit for a Self-Clocked Fair Queuing (SCFQ) Scheduler. The core objectives of the presented project is the implementation of a custom accelerator circuit that is optimized to process tag values for terabit router nodes operating at 10 Gbps per link. The system is implemented using FPGA technology and provides extended programmability to adapt the tag computation to a range of custom scheduling schemes.

Keywords

Lookup Table Traffic Type Virtual Time Weight Fair Queuing FPGA Technology 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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References

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    Mark, W., Garrett, B.: A Service Architecture for ATM: From Application to Scheduling. IEEE Network Magazine 10(3), 6–14 (1996)CrossRefGoogle Scholar
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    Choudhury, A.K., Hahne, E.L.: New implementation of multi-priority pushout for shared memory ATM switches. Computer Communications 19, 245–256 (1996)CrossRefGoogle Scholar
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    Chang, K.C.: Digital Systems Design with VHDL and Synthesis. In: An Integrated Approach. IEEE Computer Society Press and John Wiley & Sons (1999) ISBN: 0-7695-0023-4.Google Scholar
  4. 4.
    Stratix FPGA Family Data Sheet, Altera Corporation, San Jose, CA 95134, USA, Data Sheet Version 3.0 (December 2002)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2003

Authors and Affiliations

  • Brendan McAllister
    • 1
  • Sakir Sezer
    • 1
  • Ciaran Toal
    • 1
  1. 1.School of Electrical and Electronic EngineeringQueen’s University BelfastBelfastUK

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