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Quark Routing

  • Sean T. McCulloch
  • James P. Cohoon
Conference paper
  • 1.1k Downloads
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2778)

Abstract

With inherent problem complexity, ever increasing instance size and ever decreasing layout area, there is need in physical design for improved heuristics and algorithms. In this investigation, we present a novel routing methodology based on the mechanics of auctions. We demonstrate its efficacy by exhibiting the superior results of our auctionbased FPGA router QUARK on the standard benchmark suite.

Keywords

Field Programmable Gate Array Bidding Process Focus Personality Eminent Domain Multiple Personality 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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References

  1. [ALEX98]
    Alexander, M., Cohoon, J.P., Ganley, J.L., Robins, G.: Placement and Routing for High-Performance FPGA layout. In: VLSI Design: International Journal of Custom-Chip Design, Simulation, and Testing, January 1998, pp. 97–110 (1998)Google Scholar
  2. [BETZ97]
    Betz, V., Rose, J.: VPR: a new packing placement and routing tool for FPGA research. In: International Workshop on Field Programmable Logic and Application (1997)Google Scholar
  3. [Brow92]
    Brown, S.D., Rose, J.S., Vranesic, Z.G.: A detailed router for field programmable gate arrays. In: International Conference on Computer-Aided Design, pp. 382–385 (1990)Google Scholar
  4. [CHAN00]
    Chan, P.K., Schlag, M.D.F.: New parallelization and convergence results for NC: a negotiation-based FPGA route. In: International Symposium on Field Programmable Gate Arrays, pp. 165–174 (2000)Google Scholar
  5. [GAG95]
    Gagliano, R.A., Fraser, M.D., Schaefer, M.E.: Auction allocation of computing resources. Communications of the ACM, J88–J102 (June 1995)Google Scholar
  6. [Lemi93]
    Lemieux, G.G., Brown, S.D.: A detailed routing algorithm for allocating wire segments in field programmable gate arrays. In: ACM-SIGDA Physical Design Workshop (April 1993)Google Scholar
  7. [MCCU03]
    McCulloch, S.T.: Auction-based routing for FPGAs, University of Virginia, Doctoral Dissertation (2002)Google Scholar
  8. [MCMU95]
    McMurchie, L., Ebeling, C.: Pathfinder: A negotiation-based performance-driven router for FPGAs. In: International Symposium on Field Programmable Gate Arrays, pp. 111–117 (1995)Google Scholar
  9. [SHRA87]
    Shragowitz, E., Keel, S.: A global router based on a multicommodity flow model. INTEGRATION: the VLSI Journal, 3-16 (1987)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2003

Authors and Affiliations

  • Sean T. McCulloch
    • 1
  • James P. Cohoon
    • 2
  1. 1.Department of Computer ScienceOhio Wesleyan UniversityDelawareUSA
  2. 2.Department of Computer ScienceUniversity of VirginiaCharlottesvilleUSA

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